Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

13 files changed, 64 insertions, 64 deletions

diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig
index 483e3fc8a6..9323da7dd6 100644
--- a/src/mainboard/gigabyte/Kconfig
+++ b/src/mainboard/gigabyte/Kconfig
@@ -21,7 +21,7 @@
 choice
 	prompt "Mainboard model"
 	depends on VENDOR_GIGABYTE
-        
+
 source "src/mainboard/gigabyte/ga_2761gxdk/Kconfig"
 source "src/mainboard/gigabyte/ga-6bxc/Kconfig"
 source "src/mainboard/gigabyte/m57sli/Kconfig"
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
index d08414f217..728c40caf9 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
@@ -14,7 +14,7 @@ config BOARD_GIGABYTE_GA_2761GXDK
 	select LIFT_BSP_APIC_ID
 	select K8_REV_F_SUPPORT
 	select BOARD_ROMSIZE_KB_512
- 
+
 config MAINBOARD_DIR
 	string
 	default gigabyte/ga_2761gxdk
@@ -24,7 +24,7 @@ config DCACHE_RAM_BASE
 	hex
 	default 0xc8000
 	depends on BOARD_GIGABYTE_GA_2761GXDK
-	
+
 config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
@@ -36,7 +36,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE
 	depends on BOARD_GIGABYTE_GA_2761GXDK
 
 config APIC_ID_OFFSET
-	hex	
+	hex
 	default 0x10
 	depends on BOARD_GIGABYTE_GA_2761GXDK
 
@@ -76,7 +76,7 @@ config MAX_PHYSICAL_CPUS
 	depends on BOARD_GIGABYTE_GA_2761GXDK
 
 config HW_MEM_HOLE_SIZE_AUTO_INC
-	bool	
+	bool
 	default n
 	depends on BOARD_GIGABYTE_GA_2761GXDK
 
@@ -86,12 +86,12 @@ config HT_CHAIN_UNITID_BASE
 	depends on BOARD_GIGABYTE_GA_2761GXDK
 
 config HT_CHAIN_END_UNITID_BASE
-	hex	
+	hex
 	default 0x20
 	depends on BOARD_GIGABYTE_GA_2761GXDK
 
 config SERIAL_CPU_INIT
-	bool	
+	bool
 	default n
 	depends on BOARD_GIGABYTE_GA_2761GXDK
 
diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig
index 2790427080..b36261e533 100644
--- a/src/mainboard/gigabyte/m57sli/Kconfig
+++ b/src/mainboard/gigabyte/m57sli/Kconfig
@@ -17,17 +17,17 @@ config BOARD_GIGABYTE_M57SLI
 	select HAVE_ACPI_TABLES
 	select K8_REV_F_SUPPORT
 	select BOARD_ROMSIZE_KB_512
- 
+
 config MAINBOARD_DIR
 	string
-	default gigabyte/m57sli 
+	default gigabyte/m57sli
 	depends on BOARD_GIGABYTE_M57SLI
 
 config DCACHE_RAM_BASE
 	hex
 	default 0xc8000
 	depends on BOARD_GIGABYTE_M57SLI
-	
+
 config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
@@ -39,7 +39,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE
 	depends on BOARD_GIGABYTE_M57SLI
 
 config APIC_ID_OFFSET
-	hex	
+	hex
 	default 0x10
 	depends on BOARD_GIGABYTE_M57SLI
 
@@ -79,7 +79,7 @@ config MAX_PHYSICAL_CPUS
 	depends on BOARD_GIGABYTE_M57SLI
 
 config HW_MEM_HOLE_SIZE_AUTO_INC
-	bool	
+	bool
 	default n
 	depends on BOARD_GIGABYTE_M57SLI
 
@@ -89,12 +89,12 @@ config HT_CHAIN_UNITID_BASE
 	depends on BOARD_GIGABYTE_M57SLI
 
 config HT_CHAIN_END_UNITID_BASE
-	hex	
+	hex
 	default 0x20
 	depends on BOARD_GIGABYTE_M57SLI
 
 config SERIAL_CPU_INIT
-	bool	
+	bool
 	default n
 	depends on BOARD_GIGABYTE_M57SLI
 
diff --git a/src/mainboard/gigabyte/m57sli/Makefile.inc b/src/mainboard/gigabyte/m57sli/Makefile.inc
index 00075834e1..36be8066fa 100644
--- a/src/mainboard/gigabyte/m57sli/Makefile.inc
+++ b/src/mainboard/gigabyte/m57sli/Makefile.inc
@@ -1,6 +1,6 @@
 ##
 ## This file is part of the coreboot project.
-## 
+##
 ## Copyright (C) 2007-2008 coresystems GmbH
 ##
 ## This program is free software; you can redistribute it and/or modify
diff --git a/src/mainboard/gigabyte/m57sli/acpi_tables.c b/src/mainboard/gigabyte/m57sli/acpi_tables.c
index 1bd302271a..60b041a953 100644
--- a/src/mainboard/gigabyte/m57sli/acpi_tables.c
+++ b/src/mainboard/gigabyte/m57sli/acpi_tables.c
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by 
+ * ACPI FADT, FACS, and DSDT table support added by
  *
  * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
  * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
@@ -47,14 +47,14 @@ unsigned long acpi_fill_madt(unsigned long current)
 	unsigned int gsi_base = 0x18;
 	extern unsigned char bus_mcp55[8];
 	extern unsigned apicid_mcp55;
-	
+
 	unsigned sbdn;
 	struct resource *res;
 	device_t dev;
 
 	get_bus_conf();
 	sbdn = sysconf.sbdn;
-	
+
 	/* Create all subtables for processors. */
 	current = acpi_create_madt_lapics(current);
 
@@ -84,7 +84,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 	/* IRQ0 -> APIC IRQ2. */
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		current, 0, 0, 2, 0x0);	
+		current, 0, 0, 2, 0x0);
 
 	/* Create all subtables for processors. */
 	current = acpi_create_madt_lapic_nmis(current,
diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c
index 28f47597e9..8429286bc7 100644
--- a/src/mainboard/gigabyte/m57sli/ap_romstage.c
+++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c
@@ -25,7 +25,7 @@
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
-#define SET_NB_CFG_54 1 
+#define SET_NB_CFG_54 1
 
 //used by raminit
 #define QRANK_DIMM_SUPPORT 1
diff --git a/src/mainboard/gigabyte/m57sli/cmos.layout b/src/mainboard/gigabyte/m57sli/cmos.layout
index 9d37e2bba6..518f9458b6 100644
--- a/src/mainboard/gigabyte/m57sli/cmos.layout
+++ b/src/mainboard/gigabyte/m57sli/cmos.layout
@@ -1,23 +1,23 @@
-## 
+##
 ## This file is part of the coreboot project.
-## 
+##
 ## Copyright (C) 2007 AMD
 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## 
+##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
 ## (at your option) any later version.
-## 
+##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
-## 
+##
 ## You should have received a copy of the GNU General Public License
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
+##
 
 entries
 
diff --git a/src/mainboard/gigabyte/m57sli/dsdt.asl b/src/mainboard/gigabyte/m57sli/dsdt.asl
index c9b969de0e..a8c4242bff 100644
--- a/src/mainboard/gigabyte/m57sli/dsdt.asl
+++ b/src/mainboard/gigabyte/m57sli/dsdt.asl
@@ -53,7 +53,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
 			External (HCLK)
 			External (SBDN)
 			External (HCDN)
-                    
+
 			Method (_CRS, 0, NotSerialized)
                         {
 				Name (BUF0, ResourceTemplate ()
@@ -274,7 +274,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
 				Method (_CRS, 0, NotSerialized)
 				{
 					Name (BUF1, ResourceTemplate () {
-						IO (Decode16, 0x0378, 0x0378, 0x01, 0x08) 
+						IO (Decode16, 0x0378, 0x0378, 0x01, 0x08)
 						IRQNoFlags () {7}
 					})
 					Return (BUF1)
@@ -291,7 +291,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
 				Method (_CRS, 0, NotSerialized)
 				{
 					Name (BUF1, ResourceTemplate () {
-						IO (Decode16, 0x0378, 0x0378, 0x01, 0x04) 
+						IO (Decode16, 0x0378, 0x0378, 0x01, 0x04)
 						IO (Decode16, 0x0778, 0x0778, 0x01, 0x04)
 						IRQNoFlags() {7}
 						DMA (Compatibility, NotBusMaster, Transfer8) {0,1,3}
diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c
index 4d381a6e8e..cad922f16a 100644
--- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c
+++ b/src/mainboard/gigabyte/m57sli/get_bus_conf.c
@@ -39,7 +39,7 @@
         unsigned apicid_mcp55;
 
 
-unsigned pci1234x[] = 
+unsigned pci1234x[] =
 {        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
 	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
         0x0000ff0,
@@ -51,7 +51,7 @@ unsigned pci1234x[] =
 //        0x0000ff0,
 //        0x0000ff0
 };
-unsigned hcdnx[] = 
+unsigned hcdnx[] =
 { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
 	0x20202020,
 //	0x20202020,
@@ -62,7 +62,7 @@ unsigned hcdnx[] =
 //        0x20202020,
 //        0x20202020,
 };
-unsigned bus_type[256]; 
+unsigned bus_type[256];
 
 
 
@@ -95,13 +95,13 @@ void get_bus_conf(void)
 	for(i=0; i<8; i++) {
 		bus_mcp55[i] = 0;
 	}
-	
+
 	for(i=0;i<256; i++) {
 		bus_type[i] = 0;
 	}
 
 	bus_type[0] = 1; //pci
-	
+
 	bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
 
 	bus_type[bus_mcp55[0]] = 1;
@@ -139,8 +139,8 @@ void get_bus_conf(void)
 /*I/O APICs:	APIC ID	Version	State		Address*/
 #if CONFIG_LOGICAL_CPUS==1
 	apicid_base = get_apicid_base(1);
-#else 
-	apicid_base = CONFIG_MAX_PHYSICAL_CPUS; 
+#else
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
 #endif
 	apicid_mcp55 = apicid_base+0;
 
diff --git a/src/mainboard/gigabyte/m57sli/irq_tables.c b/src/mainboard/gigabyte/m57sli/irq_tables.c
index 5cb6d8420c..bc6aded97f 100644
--- a/src/mainboard/gigabyte/m57sli/irq_tables.c
+++ b/src/mainboard/gigabyte/m57sli/irq_tables.c
@@ -19,7 +19,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* This file was generated by getpir.c, do not modify! 
+/* This file was generated by getpir.c, do not modify!
    (but if you do, please run checkpir on it to verify)
    Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
 
@@ -33,11 +33,11 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, 
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
 		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
 		uint8_t slot, uint8_t rfu)
 {
-        pirq_info->bus = bus; 
+        pirq_info->bus = bus;
         pirq_info->devfn = devfn;
                 pirq_info->irq[0].link = link0;
                 pirq_info->irq[0].bitmap = bitmap0;
@@ -79,15 +79,15 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
-	
+
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version  = PIRQ_VERSION;
-	
+
 	pirq->rtr_bus = bus_mcp55[0];
 	pirq->rtr_devfn = ((sbdn+6)<<3)|0;
 
 	pirq->exclusive_irqs = 0;
-	
+
 	pirq->rtr_vendor = 0x10de;
 	pirq->rtr_device = 0x0370;
 
@@ -100,11 +100,11 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 //pci bridge
 	write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 	pirq_info++; slot_num++;
-        
-	pirq->size = 32 + 16 * slot_num; 
+
+	pirq->size = 32 + 16 * slot_num;
 
         for (i = 0; i < pirq->size; i++)
-                sum += v[i];	
+                sum += v[i];
 
 	sum = pirq->checksum - sum;
 
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index 93e6c274c9..3aad7e281f 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -32,7 +32,7 @@ extern unsigned char bus_mcp55[8]; //1
 
 extern unsigned apicid_mcp55;
 
-extern unsigned bus_type[256]; 
+extern unsigned bus_type[256];
 
 
 
@@ -94,7 +94,7 @@ static void *smp_write_config_table(void *v)
                 }
 	}
 
-	/*I/O Ints:	     Type	Trigger    Polarity	                  Bus ID   IRQ	APIC ID	      PIN# */	
+	/*I/O Ints:	     Type	Trigger    Polarity	                  Bus ID   IRQ	APIC ID	      PIN# */
 	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0);
 
 /* ISA ints are edge-triggered, and usually originate from the ISA bus,
@@ -122,7 +122,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\
 			 bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin))
 
-	PCI_INT(0,sbdn+1,1, 10); /* SMBus */ 
+	PCI_INT(0,sbdn+1,1, 10); /* SMBus */
 	PCI_INT(0,sbdn+2,0, 22); /* USB */
 	PCI_INT(0,sbdn+2,1, 23); /* USB */
 	PCI_INT(0,sbdn+4,0, 21); /* IDE */
@@ -144,8 +144,8 @@ static void *smp_write_config_table(void *v)
         }
 
 	/* On bus 1: the PCI bus slots...
-	   pyhsical PCI slots are j = 7,8 
-	   FireWire is j = 10		
+	   pyhsical PCI slots are j = 7,8
+	   FireWire is j = 10
 	*/
         k=2;
         for(i=0; i<4; i++){
diff --git a/src/mainboard/gigabyte/m57sli/resourcemap.c b/src/mainboard/gigabyte/m57sli/resourcemap.c
index 847cd86e65..43ff3ed11a 100644
--- a/src/mainboard/gigabyte/m57sli/resourcemap.c
+++ b/src/mainboard/gigabyte/m57sli/resourcemap.c
@@ -161,7 +161,7 @@ static void setup_mb_resource_map(void)
 		 *	   1 = base/limit registers i are read-only
 		 * [ 7: 4] Reserved
 		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-		 *	   This field defines the upper address bits of a 40bit address 
+		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
 		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
@@ -199,7 +199,7 @@ static void setup_mb_resource_map(void)
 		 * [31:25] Reserved
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
-		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
 
@@ -217,7 +217,7 @@ static void setup_mb_resource_map(void)
 		 * [ 3: 2] Reserved
 		 * [ 4: 4] VGA Enable
 		 *	   0 = VGA matches Disabled
-		 *	   1 = matches all address < 64K and where A[9:0] is in the 
+		 *	   1 = matches all address < 64K and where A[9:0] is in the
 		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 		 * [ 5: 5] ISA Enable
 		 *	   0 = ISA matches Disabled
@@ -225,7 +225,7 @@ static void setup_mb_resource_map(void)
 		 *	       from matching agains this base/limit pair
 		 * [11: 6] Reserved
 		 * [24:12] PCI I/O Base i
-		 *	   This field defines the start of PCI I/O region n 
+		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
@@ -270,9 +270,9 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the highest bus number in configuration region i
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
-		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 
 	};
 
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 1e3bee8845..3f2f5e6f53 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -39,7 +39,7 @@
 #endif
 
 #define DBGP_DEFAULT 7
- 
+
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -123,7 +123,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
 
-#include "resourcemap.c" 
+#include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
 
@@ -142,13 +142,13 @@ static void sio_setup(void)
         uint8_t byte;
 
         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
+        byte |= 0x20;
         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-        
+
         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
         dword |= (1<<0);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-        
+
         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
         dword |= (1<<16);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
@@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
 	};
 
-        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE 
+        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset = 0;
@@ -209,7 +209,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         setup_mb_resource_map();
 
         uart_init();
-	
+
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
@@ -281,7 +281,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         //It's the time to set ctrl in sysinfo now;
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 
-        enable_smbus(); 
+        enable_smbus();
 
         /* all ap stopped? */