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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-03-18 20:58:41 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-03-18 20:58:41 +0000
commit78acf932912669eb0eb7f7280da1b3c550035ebb (patch)
tree89f13a87df362395527d41f42d0a57a167eab8db /src/mainboard/gigabyte
parent2bd91003413d431f0a4db6c3c6691f4b688cf5c5 (diff)
Remove remaining uses of
HAVE_FAILOVER_BOOT HAVE_FALLBACK_BOOT USE_FAILOVER_IMAGE USE_FALLBACK_IMAGE Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/gigabyte')
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/Kconfig10
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/romstage.c11
-rw-r--r--src/mainboard/gigabyte/m57sli/Kconfig10
-rw-r--r--src/mainboard/gigabyte/m57sli/romstage.c11
4 files changed, 0 insertions, 42 deletions
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
index 348139b501..9873d6d431 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
@@ -75,16 +75,6 @@ config PCI_64BIT_PREF_MEM
default n
depends on BOARD_GIGABYTE_GA_2761GXDK
-config HAVE_FALLBACK_BOOT
- bool
- default n
- depends on BOARD_GIGABYTE_GA_2761GXDK
-
-config USE_FALLBACK_IMAGE
- bool
- default n
- depends on BOARD_GIGABYTE_GA_2761GXDK
-
config HW_MEM_HOLE_SIZEK
hex
default 0x100000
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 0444e49166..1819b901c8 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -56,7 +56,6 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
-#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#if CONFIG_USBDEBUG_DIRECT
@@ -73,15 +72,11 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8716f/it8716f_early_serial.c"
#include "superio/ite/it8716f/it8716f_early_init.c"
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@@ -150,8 +145,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c"
-#endif
-
#include "northbridge/amd/amdk8/early_ht.c"
@@ -175,8 +168,6 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword);
}
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
@@ -303,5 +294,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
-
-#endif
diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig
index 098312cc9a..5a4f0a7dc7 100644
--- a/src/mainboard/gigabyte/m57sli/Kconfig
+++ b/src/mainboard/gigabyte/m57sli/Kconfig
@@ -78,16 +78,6 @@ config PCI_64BIT_PREF_MEM
default n
depends on BOARD_GIGABYTE_M57SLI
-config HAVE_FALLBACK_BOOT
- bool
- default n
- depends on BOARD_GIGABYTE_M57SLI
-
-config USE_FALLBACK_IMAGE
- bool
- default n
- depends on BOARD_GIGABYTE_M57SLI
-
config HW_MEM_HOLE_SIZEK
hex
default 0x100000
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index bd67ab9595..4226ac3614 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -54,7 +54,6 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
-#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#if CONFIG_USBDEBUG_DIRECT
@@ -70,15 +69,11 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8716f/it8716f_early_serial.c"
#include "superio/ite/it8716f/it8716f_early_init.c"
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@@ -148,8 +143,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c"
-#endif
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -175,8 +168,6 @@ static void sio_setup(void)
}
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
@@ -316,5 +307,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
-
-#endif