diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-19 09:46:33 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-20 21:54:45 +0200 |
| commit | 531b87ac4e8038aedf9c44c29fe2c1fc31adb346 (patch) | |
| tree | 0beaa7220a61927e2bc0a4d59eb1827b73fe6c02 /src/mainboard/gigabyte/m57sli | |
| parent | 04f8fd981fd49e9929fea2b27991e78673fc57a3 (diff) | |
src/mainboard/getac - kontron: Add space around operators
Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/gigabyte/m57sli')
| -rw-r--r-- | src/mainboard/gigabyte/m57sli/fanctl.c | 2 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/m57sli/mptable.c | 14 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/m57sli/romstage.c | 8 |
3 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/gigabyte/m57sli/fanctl.c b/src/mainboard/gigabyte/m57sli/fanctl.c index 07a2666cdf..cc0cdcac23 100644 --- a/src/mainboard/gigabyte/m57sli/fanctl.c +++ b/src/mainboard/gigabyte/m57sli/fanctl.c @@ -75,7 +75,7 @@ static const struct { void init_ec(uint16_t base) { int i; - for (i=0; i<ARRAY_SIZE(sequence); i++) { + for (i = 0; i < ARRAY_SIZE(sequence); i++) { write_index(base, sequence[i].index, sequence[i].value); } } diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c index e6cb28bb71..403b96952c 100644 --- a/src/mainboard/gigabyte/m57sli/mptable.c +++ b/src/mainboard/gigabyte/m57sli/mptable.c @@ -84,9 +84,9 @@ static void *smp_write_config_table(void *v) /* The PCIe slots, each on its own bus */ k = 1; - for(i=0; i<4; i++){ - for(j=7; j>1; j--){ - if(k>3) k=0; + for(i = 0; i < 4; i++){ + for(j = 7; j > 1; j--){ + if(k > 3) k = 0; PCI_INT(j,0,i, 16+k); k++; } @@ -97,10 +97,10 @@ static void *smp_write_config_table(void *v) physical PCI slots are j = 7,8 FireWire is j = 10 */ - k=2; - for(i=0; i<4; i++){ - for(j=6; j<11; j++){ - if(k>3) k=0; + k = 2; + for(i = 0; i < 4; i++){ + for(j = 6; j < 11; j++){ + if(k > 3) k = 0; PCI_INT(1,j,i, 16+k); k++; } diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index b1c849b9bb..f8d12c6b2c 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -80,11 +80,11 @@ static void sio_setup(void) pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); + dword |= (1 << 0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); + dword |= (1 << 16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } @@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif |