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authorAngel Pons <th3fanbus@gmail.com>2019-12-05 00:12:38 +0100
committerNico Huber <nico.h@gmx.de>2020-03-07 18:40:32 +0000
commit11bf9df9ac73449d3291e927771abbbbcd4af145 (patch)
treea617a3cecc9933f307b587d7a4498a48191a2f87 /src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb
parentffcf641cc4cb9fc5b8a49599d001fbe180dea6fa (diff)
mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant
Took less than 30 minutes, and booted on the first try :) Working: - Native raminit, using two 2GB DDR3-1333 DIMMs - S3 suspend/resume - USB ports and headers - EHCI Debug with an FT2232H - Gigabit Ethernet - Integrated DVI/VGA outputs (libgfxinit) - PCIe x16 for a graphics card - PCIe x1 ports - PS/2 port with a keyboard - SATA controller - Audio outputs, both front and rear - flashrom, using the internal programmer. Tested with coreboot, as well as with the vendor firmware. Backup chip is untested. Untested: - VGA BIOS for integrated graphics init - Audio inputs - Non-Linux OSes - ACPI thermal zone and OS-independent fan control Not working: - Default IFD defines the BIOS region as the entire flash chip. Using 'flashrom --ifd -i bios' is asking for a failed flash! Change-Id: I467f586530e4a3b53a24b66565b5dcab5e33cf46 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb')
-rw-r--r--src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb96
1 files changed, 96 insertions, 0 deletions
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb
new file mode 100644
index 0000000000..2cc5b19651
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb
@@ -0,0 +1,96 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Angel Pons <th3fanbus@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/sandybridge
+ device cpu_cluster 0 on
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0 on end
+ device lapic 0xacac off end
+ end
+ end
+ register "pci_mmio_size" = "2048"
+ device domain 0 on
+ subsystemid 0x1458 0x5000 inherit
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PEG
+ device pci 02.0 on end # iGPU
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "gen1_dec" = "0x003c0a01"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x33"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+
+ device pci 16.0 on end # MEI #1
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # HD Audio
+
+ device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1_3)
+ device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1)
+ device pci 1c.2 off end # RP #3:
+ device pci 1c.3 off end # RP #4:
+ device pci 1c.4 on end # RP #4: Realtek RTL8111F GbE NIC
+ device pci 1c.5 on end # RP #5: PCIe x1 Port (PCIEX1_2)
+
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ chip superio/ite/it8728f
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 off end # COM1
+ device pnp 2e.2 off end # COM2
+ device pnp 2e.3 off end # Parallel port
+ device pnp 2e.4 on # Environment Controller
+ io 0x60 = 0x0a30
+ io 0x62 = 0x0a20
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ end
+ device pnp 2e.6 on end # Mouse
+ device pnp 2e.7 on # GPIO
+ irq 0x25 = 0x40
+ irq 0x26 = 0xf7
+ irq 0x27 = 0x10
+ irq 0x2c = 0x80
+ io 0x60 = 0x0000
+ io 0x62 = 0x0a00
+ io 0x64 = 0x0000
+ irq 0x73 = 0x00
+ irq 0xc1 = 0x37
+ irq 0xcb = 0x00
+ irq 0xf0 = 0x10
+ irq 0xf1 = 0x42
+ irq 0xf6 = 0x1c
+ end
+ device pnp 2e.a off end # CIR
+ end
+ end
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 on end # Thermal
+ end
+ end
+end