diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 19:11:50 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-18 11:48:35 +0000 |
commit | fa5d0f835b1f3bb8907e616913cbf7b91d09ef26 (patch) | |
tree | af8d33b500b91fa9e2f1a76d9115086644ccf3d2 /src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c | |
parent | 59eb2fdb6b06618311ef118996ca8c1d28a85ffc (diff) |
nb/intel/sandybridge: Set up console in bootblock
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c')
-rw-r--r-- | src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c | 58 |
1 files changed, 0 insertions, 58 deletions
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c deleted file mode 100644 index a68070fbe6..0000000000 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <northbridge/intel/sandybridge/sandybridge.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8728f/it8728f.h> - -#define SUPERIO_GPIO PNP_DEV(0x2e, IT8728F_GPIO) -#define SERIAL_DEV PNP_DEV(0x2e, 0x01) - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - -void mainboard_config_superio(void) -{ - if (!CONFIG(NO_UART_ON_SUPERIO)) { - /* Enable serial port */ - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - } - - /* Disable SIO WDT which kicks in DualBIOS */ - ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E); -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} |