mb/gigabyte/ga-h61m-s2pv: Add new mainboard

Tested with GRUB 2.02 as a payload, booting Arch Linux with
latest kernel. This code is based on the output of autoport
as well as existing ga-b75m-d3h and ga-b75m-d3v mainboards.

Working:
 - Serial port I/O
 - S3 suspend/resume (broken with SeaBIOS 1.11.1)
 - USB ports and headers
 - Gigabit Ethernet
 - Integrated graphics (libgfxinit)
 - PCIe x16 graphics
 - PCIe x1
 - SATA controller
 - Hardware Monitor
 - Fan Control (fancontrol on linux works well)
 - Native raminit (4+4GB, 4+2GB, 2+2GB, DDR3-1333)
 - Native graphics init with libgfxinit
 - flashrom, using the internal programmer. Tested with coreboot,
   as well as with the vendor firmware. Backup chip is untested.
 - NVRAM settings. Only `gfx_uma_size` and `debug_level` have been
   tested with values different from the default.

Untested:
 - VGA BIOS for integrated graphics init
 - DVI port. It can detect a "fake" display, that is, an
   EEPROM connected to the DVI port.
 - PS/2 ports
 - Audio: Only rear output (green) has been tested.
 - EHCI debug.
 - Parallel port
 - Non-Linux OSes
 - ACPI thermal zone and fan control (probably not working)

Not working:
 - SATA devices with Tianocore (payload issue)
 - PCIe to PCI bridge. It seems to be poorly supported on Linux,
   it lacks a public datasheet and vendor BIOS behaves in the
   same way: The bridge and the devices behind it appear, but
   drivers fail to find devices attached to the bridge.

Change-Id: I598a0b75093a0f1aef2ac615035d66786a8c22cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/25912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

1 files changed, 71 insertions, 0 deletions

diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
new file mode 100644
index 0000000000..3e63721bd3
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
+#define SUPERIO_GPIO PNP_DEV(0x2e, IT8728F_GPIO)
+#define SERIAL_DEV PNP_DEV(0x2e, 0x01)
+
+void pch_enable_lpc(void)
+{
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
+			CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
+
+	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+}
+
+void mainboard_rcba_config(void)
+{
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 0, 0 },
+	{ 1, 0, 0 },
+	{ 1, 0, 1 },
+	{ 1, 0, 1 },
+	{ 1, 0, 2 },
+	{ 1, 0, 2 },
+	{ 1, 0, 3 },
+	{ 1, 0, 3 },
+	{ 1, 0, 4 },
+	{ 1, 0, 4 },
+	{ 1, 0, 6 },
+	{ 1, 0, 5 },
+	{ 1, 0, 5 },
+	{ 1, 0, 6 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+	/* Enable serial port and flip some magic bits */
+
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+	ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E); // magic
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+}