diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-10-24 00:57:54 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-25 21:23:06 +0200 |
| commit | 64e341ec1654645b77c9ec158b01fb992a44b882 (patch) | |
| tree | 918296e7585f8106a73afaa0e55942eb45037c14 /src/mainboard/gigabyte/ga-g41m-es2l | |
| parent | c057a0611b9f5bb66ad3bd54890991eec7838192 (diff) | |
mb/ga-g41m-es2l: remove unneeded IGD IRQ setting in ACPI
According to: "Intel ® 4 Series Chipset Family datasheet"
the IGD only has 1 IRQ pin.
Change-Id: I974f002f5a213056f4593a1eab10772527bb241d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17098
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/gigabyte/ga-g41m-es2l')
| -rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl index aa617ea468..46e8a4af5a 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl @@ -24,9 +24,6 @@ Method(_PRT) Package() { 0x0001ffff, 0, 0, 16 }, /* Internal GFX */ Package() { 0x0002ffff, 0, 0, 16 }, - Package() { 0x0002ffff, 1, 0, 17 }, - Package() { 0x0002ffff, 2, 0, 18 }, - Package() { 0x0002ffff, 3, 0, 19 }, /* High Definition Audio 0:1b.0 */ Package() { 0x001bffff, 0, 0, 16 }, /* PCIe Root Ports 0:1c.x */ @@ -52,9 +49,6 @@ Method(_PRT) Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, /* Internal GFX */ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, /* High Definition Audio 0:1b.0 */ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, /* PCIe Root Ports 0:1c.x */ |