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| author | Lijian Zhao <lijian.zhao@intel.com> | 2019-01-15 17:37:50 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-01-16 21:45:40 +0000 |
| commit | c3e75b42a471cc64fec37a464eef7088492ec04e (patch) | |
| tree | c2d248aa53d85e6db5110056e94b8bf42a98a0da /src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | |
| parent | 314094fea6e91a99f1d971c406d871a8b925fbce (diff) | |
soc/intel/cannonlake: Fix afterg3 programming
According to EDS #565870 chapter 5.3.1, AG3E bit in PMC located in PMC
memory mapped register but not pci config spaces. Change the programming
to affect that difference.
BUG=b:122425492
TEST=Change System Power State after failure to "s5 off", and boot up
onto sarien platform, check the register with iotools mmio_read32
0xfe001020 and bit 0 is set.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I0934894558fd9cbc056dea8e7ac30426c2529e4e
Reviewed-on: https://review.coreboot.org/c/30945
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb')
0 files changed, 0 insertions, 0 deletions