mb/gigabyte: Add GA-D510UD

Booted fine on the first try. Most things work properly, but I haven't
tested them thoroughly. Native raminit chokes with a DIMM in the second
slot, but the first slot works properly.

Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

16 files changed, 469 insertions, 0 deletions

diff --git a/src/mainboard/gigabyte/ga-d510ud/Kconfig b/src/mainboard/gigabyte/ga-d510ud/Kconfig
new file mode 100644
index 0000000000..71fe981d7d
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/Kconfig
@@ -0,0 +1,27 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_GIGABYTE_GA_D510UD
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_512
+	select CPU_INTEL_SOCKET_FCBGA559
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select NORTHBRIDGE_INTEL_PINEVIEW
+	select REALTEK_8168_RESET
+	select SOUTHBRIDGE_INTEL_I82801GX
+	select SUPERIO_ITE_IT8720F
+
+config MAINBOARD_DIR
+	string
+	default "gigabyte/ga-d510ud"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "GA-D510UD"
+
+endif # BOARD_GIGABYTE_GA_D510UD
diff --git a/src/mainboard/gigabyte/ga-d510ud/Kconfig.name b/src/mainboard/gigabyte/ga-d510ud/Kconfig.name
new file mode 100644
index 0000000000..68c6dc4db1
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GIGABYTE_GA_D510UD
+	bool "GA-D510UD"
diff --git a/src/mainboard/gigabyte/ga-d510ud/Makefile.inc b/src/mainboard/gigabyte/ga-d510ud/Makefile.inc
new file mode 100644
index 0000000000..e78c424e43
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/Makefile.inc
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += early_init.c
+
+romstage-y += early_init.c
+romstage-y += gpio.c
+
+ramstage-y += cstates.c
diff --git a/src/mainboard/gigabyte/ga-d510ud/acpi/ec.asl b/src/mainboard/gigabyte/ga-d510ud/acpi/ec.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/acpi/ec.asl
diff --git a/src/mainboard/gigabyte/ga-d510ud/acpi/ich7_pci_irqs.asl b/src/mainboard/gigabyte/ga-d510ud/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000000..d6e6bef668
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* This is the IRQ routing for the 0:1e.0 PCI bridge of the NM10 */
+
+If (PICM) {
+	Return (Package() {
+		Package() { 0x0000ffff, 0, 0, 0x15},
+		Package() { 0x0000ffff, 1, 0, 0x16},
+		Package() { 0x0000ffff, 2, 0, 0x17},
+		Package() { 0x0000ffff, 3, 0, 0x14},
+		Package() { 0x0001ffff, 0, 0, 0x13},
+	})
+} Else {
+	Return (Package() {
+		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
+	})
+}
diff --git a/src/mainboard/gigabyte/ga-d510ud/acpi/superio.asl b/src/mainboard/gigabyte/ga-d510ud/acpi/superio.asl
new file mode 100644
index 0000000000..c67e5d8e81
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/acpi/superio.asl
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#undef SUPERIO_DEV
+#undef SUPERIO_PNP_BASE
+#undef IT8720F_SHOW_SP1
+#undef IT8720F_SHOW_SP2
+#undef IT8720F_SHOW_EC
+#undef IT8720F_SHOW_KBCK
+#undef IT8720F_SHOW_KBCM
+#define SUPERIO_DEV		SIO0
+#define SUPERIO_PNP_BASE	0x2e
+#define IT8720F_SHOW_SP1
+#define IT8720F_SHOW_SP2
+#define IT8720F_SHOW_EC
+#define IT8720F_SHOW_KBCK
+#define IT8720F_SHOW_KBCM
+#include <superio/ite/it8720f/acpi/superio.asl>
diff --git a/src/mainboard/gigabyte/ga-d510ud/board_info.txt b/src/mainboard/gigabyte/ga-d510ud/board_info.txt
new file mode 100644
index 0000000000..ad5afe1a2e
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/board_info.txt
@@ -0,0 +1,6 @@
+Category: mini
+Board URL: https://www.gigabyte.com/Motherboard/GA-D510UD-rev-10
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/gigabyte/ga-d510ud/cmos.default b/src/mainboard/gigabyte/ga-d510ud/cmos.default
new file mode 100644
index 0000000000..41098be2bb
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/cmos.default
@@ -0,0 +1,5 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+gfx_uma_size=8M
diff --git a/src/mainboard/gigabyte/ga-d510ud/cmos.layout b/src/mainboard/gigabyte/ga-d510ud/cmos.layout
new file mode 100644
index 0000000000..1e08c1f9b0
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/cmos.layout
@@ -0,0 +1,67 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	6	debug_level
+
+# coreboot config options: southbridge
+408	1	e	1	nmi
+409	2	e	7	power_on_after_fail
+
+# coreboot config options: bootloader
+416	512	s	0	boot_devices
+
+# coreboot config options: cpu
+
+# coreboot config options: northbridge
+952	3	e	11	gfx_uma_size
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+1	0	Disable
+1	1	Enable
+2	0	Enable
+2	1	Disable
+4	0	Fallback
+4	1	Normal
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+7	0	Disable
+7	1	Enable
+7	2	Keep
+11	0	8M
+11	1	16M
+11	2	32M
+11	3	48M
+11	4	64M
+11	5	128M
+11	6	256M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/gigabyte/ga-d510ud/cstates.c b/src/mainboard/gigabyte/ga-d510ud/cstates.c
new file mode 100644
index 0000000000..21b18b9e8d
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/cstates.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen.h>
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+	return 0;
+}
diff --git a/src/mainboard/gigabyte/ga-d510ud/data.vbt b/src/mainboard/gigabyte/ga-d510ud/data.vbt
new file mode 100644
index 0000000000..ae75a25362
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/data.vbt
diff --git a/src/mainboard/gigabyte/ga-d510ud/devicetree.cb b/src/mainboard/gigabyte/ga-d510ud/devicetree.cb
new file mode 100644
index 0000000000..9fb5ff52c3
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/devicetree.cb
@@ -0,0 +1,80 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/pineview
+	register "use_crt"  = "1"
+
+	device cpu_cluster 0 on
+		chip cpu/intel/socket_FCBGA559
+			device lapic 0 on end
+		end
+	end
+	device domain 0 on
+		subsystemid 0x105b 0x0d55 inherit
+		device pci 0.0 on  end		# Host Bridge
+		device pci 2.0 on  end		# iGPU
+		device pci 2.1 off end		# iGPU 2
+
+		chip southbridge/intel/i82801gx
+			register "pirqa_routing" = "0x0b"
+			register "pirqb_routing" = "0x0b"
+			register "pirqc_routing" = "0x0b"
+			register "pirqd_routing" = "0x0b"
+			register "pirqe_routing" = "0x0b"
+			register "pirqf_routing" = "0x0b"
+			register "pirqg_routing" = "0x0b"
+			register "pirqh_routing" = "0x0b"
+
+			register "sata_ports_implemented" = "0x3"
+			register "gpe0_en" = "0x441"
+
+			register "gen1_dec" = "0x00040291" # Environment Controller
+
+			device pci 1b.0 on  end		# HD Audio
+			device pci 1c.0 on  end		# PCIe 1: Realtek GbE NIC
+			device pci 1c.1 on  end		# PCIe 2: JMB363 SATA/IDE
+			device pci 1c.2 off end		# PCIe 3
+			device pci 1c.3 off end		# PCIe 4
+			device pci 1d.0 on  end		# UHCI
+			device pci 1d.1 on  end		# UHCI
+			device pci 1d.2 on  end		# UHCI
+			device pci 1d.3 on  end		# UHCI
+			device pci 1d.7 on  end		# EHCI
+			device pci 1e.0 on  end		# PCI bridge
+			device pci 1f.0 on		# LPC bridge
+				chip superio/ite/it8720f
+					device pnp 2e.0 off end	# Floppy
+					device pnp 2e.1 on	# COM1
+						io  0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.2 on	# COM2
+						io  0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.3 on	 # PP
+						io  0x60 = 0x378
+						io  0x62 = 0
+						irq 0x70 = 7
+					end
+					device pnp 2e.4 on	# EC
+						io  0x60 = 0x0290
+						io  0x62 = 0
+						irq 0x70 = 0
+					end
+					device pnp 2e.5 on	# PS/2 keyboard
+						io  0x60 = 0x60
+						io  0x62 = 0x64
+						irq 0x70 = 1
+					end
+					device pnp 2e.6 on	# PS/2 mouse
+						irq 0x70 = 12
+					end
+					device pnp 2e.7 off end	# GPIO
+					device pnp 2e.a off end	# CIR
+				end
+			end
+			device pci 1f.2 on  end		# SATA
+			device pci 1f.3 on  end		# SMbus
+		end
+	end
+end
diff --git a/src/mainboard/gigabyte/ga-d510ud/dsdt.asl b/src/mainboard/gigabyte/ga-d510ud/dsdt.asl
new file mode 100644
index 0000000000..0e2fa7bb6e
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/dsdt.asl
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20090419
+)
+{
+	#include <acpi/dsdt_top.asl>
+
+	#include <southbridge/intel/common/acpi/platform.asl>
+	#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+
+	#include <cpu/intel/speedstep/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <northbridge/intel/pineview/acpi/pineview.asl>
+		#include <southbridge/intel/i82801gx/acpi/ich7.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/gigabyte/ga-d510ud/early_init.c b/src/mainboard/gigabyte/ga-d510ud/early_init.c
new file mode 100644
index 0000000000..8fdf25db65
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/early_init.c
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/pineview/pineview.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8720f/it8720f.h>
+
+#define SERIAL_DEV	PNP_DEV(0x2e, IT8720F_SP1)
+#define GPIO_DEV	PNP_DEV(0x2e, IT8720F_GPIO)
+#define EC_DEV		PNP_DEV(0x2e, IT8720F_EC)
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Set default GPIOs on superio */
+	pnp_enter_conf_state(GPIO_DEV);
+
+	pnp_set_logical_device(GPIO_DEV);
+	pnp_write_config(GPIO_DEV, 0x25, 0x00);
+	pnp_write_config(GPIO_DEV, 0x26, 0x0c);
+	pnp_write_config(GPIO_DEV, 0x28, 0x41);
+	pnp_write_config(GPIO_DEV, 0x2c, 0x01);
+	pnp_write_config(GPIO_DEV, 0x62, 0x08);
+	pnp_write_config(GPIO_DEV, 0x72, 0x00);
+	pnp_write_config(GPIO_DEV, 0xb8, 0x00);
+	pnp_write_config(GPIO_DEV, 0xc0, 0x00);
+	pnp_write_config(GPIO_DEV, 0xc1, 0x0c);
+	pnp_write_config(GPIO_DEV, 0xc3, 0x41);
+	pnp_write_config(GPIO_DEV, 0xc8, 0x00);
+	pnp_write_config(GPIO_DEV, 0xcb, 0x00);
+	pnp_write_config(GPIO_DEV, 0xe9, 0x01);
+	pnp_write_config(GPIO_DEV, 0xfc, 0xa4);
+
+	pnp_exit_conf_state(GPIO_DEV);
+
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+	pnp_enter_conf_state(GPIO_DEV);
+	pnp_set_logical_device(GPIO_DEV);
+
+	printk(BIOS_DEBUG, "ITE register 0xef: 0x%02x ", pnp_read_config(GPIO_DEV, 0xef));
+
+	/* Disable SIO reboot */
+	pnp_write_config(GPIO_DEV, 0xef, 0x7e);
+
+	printk(BIOS_DEBUG, "=> 0x%02x\n", pnp_read_config(GPIO_DEV, 0xef));
+
+	pnp_set_logical_device(EC_DEV);
+	pnp_write_config(EC_DEV, 0x70, 0x00); /* Don't use IRQ9 */
+	pnp_write_config(EC_DEV, 0x30, 0x01); /* Enable */
+
+	pnp_exit_conf_state(GPIO_DEV);
+}
+
+void get_mb_spd_addrmap(u8 *spd_addrmap)
+{
+	spd_addrmap[0] = 0x50;
+	spd_addrmap[1] = 0x51;
+}
diff --git a/src/mainboard/gigabyte/ga-d510ud/gpio.c b/src/mainboard/gigabyte/ga-d510ud/gpio.c
new file mode 100644
index 0000000000..5c756b9cfa
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/gpio.c
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_NATIVE,
+	.gpio1 = GPIO_MODE_NATIVE,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_NATIVE,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_GPIO,
+	.gpio10 = GPIO_MODE_GPIO,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_NATIVE,
+	.gpio17 = GPIO_MODE_NATIVE,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_GPIO,
+	.gpio21 = GPIO_MODE_NATIVE,
+	.gpio22 = GPIO_MODE_NATIVE,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_GPIO,
+	.gpio26 = GPIO_MODE_GPIO,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_NATIVE,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio9 = GPIO_DIR_INPUT,
+	.gpio10 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio20 = GPIO_DIR_OUTPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio25 = GPIO_DIR_INPUT,
+	.gpio26 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_OUTPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio20 = GPIO_LEVEL_HIGH,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio26 = GPIO_LEVEL_LOW,
+	.gpio27 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio6 = GPIO_INVERT,
+	.gpio7 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+	.gpio11 = GPIO_INVERT,
+	.gpio12 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_NATIVE,
+	.gpio36 = GPIO_MODE_NATIVE,
+	.gpio37 = GPIO_MODE_NATIVE,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio33 = GPIO_LEVEL_HIGH,
+	.gpio34 = GPIO_LEVEL_LOW,
+	.gpio38 = GPIO_LEVEL_HIGH,
+	.gpio39 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.invert		= &pch_gpio_set1_invert,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+	},
+};
diff --git a/src/mainboard/gigabyte/ga-d510ud/hda_verb.c b/src/mainboard/gigabyte/ga-d510ud/hda_verb.c
new file mode 100644
index 0000000000..f36d48cfb5
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-d510ud/hda_verb.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0662,
+	0x105b0d55,	/* Subsystem ID */
+	10,		/* Number of entries */
+
+	/* Pin Widget Verb Table */
+	AZALIA_PIN_CFG(0, 0x14, 0x01014c10),
+	AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19c30),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19c31),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181343f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214c1f),
+	AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4005c603),
+	AZALIA_PIN_CFG(0, 0x1e, 0x99430120),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;