mb/gigabyte/ga-{h61m-s2pv,b75m-d3h,b75m-d3v}: Clean up mainboard code

I ported ga-h61m-s2pv based on the two Gigabyte b75m boards.
Based on another mainboard's code review comments, this patch
improves the code quality of these three similar boards.

ga-h61m-s2pv is tested and confirmed to be working, but I cannot
say the same regarding the other two mainboards as I do not have them.

Change-Id: Ib7747cceb5ba56f791677204cdc4c54c129c70c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

1 files changed, 34 insertions, 53 deletions

diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
index a389e68f0d..1ca6551cc5 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
@@ -13,53 +13,16 @@
  * GNU General Public License for more details.
  */
 
-#define SUPERIO_BASE 0x2e
-#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0)
-#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
-#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
-
-#include <arch/io.h>
-#include <device/pci_def.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <arch/acpi.h>
-#include <console/console.h>
-#include <superio/ite/it8728f/it8728f.h>
-#include <superio/ite/common/ite.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
-#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
-
-static void it8728f_b75md3v_disable_reboot(pnp_devfn_t dev)
-{
-	/* GPIO SIO settings */
-	ite_reg_write(dev, 0xEF, 0x7E); // magic
-
-	ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16
-	ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34
-	ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port
-	ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00
-	ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear!
-	ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear!
-	ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in
-	ite_reg_write(dev, 0xe9, 0x27); // bus select disable
-	ite_reg_write(dev, 0xf0, 0x10); // ?
-	ite_reg_write(dev, 0xf1, 0x42); // ?
-	ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12)
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
 
-	/* EC SIO settings */
-	ite_reg_write(IT8728F_EC, 0xf1, 0xc0);
-	ite_reg_write(IT8728F_EC, 0xf6, 0xf0);
-	ite_reg_write(IT8728F_EC, 0xf9, 0x48);
-	ite_reg_write(IT8728F_EC, 0x60, 0x0a);
-	ite_reg_write(IT8728F_EC, 0x61, 0x30);
-	ite_reg_write(IT8728F_EC, 0x62, 0x0a);
-	ite_reg_write(IT8728F_EC, 0x63, 0x20);
-	ite_reg_write(IT8728F_EC, 0x30, 0x01);
-}
+#define SUPERIO_BASE 0x2e
+#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0)
+#define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
+#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
 
 void mainboard_rcba_config(void)
 {
@@ -69,14 +32,7 @@ void mainboard_rcba_config(void)
 
 void pch_enable_lpc(void)
 {
-	/*
-	 * Enable:
-	 *  EC Decode Range PortA30/A20
-	 *  SuperIO Port2E/2F
-	 *  PS/2 Keyboard/Mouse Port60/64
-	 *  FDD Port3F0h-3F5h and Port3F7h
-	 */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
 			CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
 
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
@@ -86,7 +42,31 @@ void pch_enable_lpc(void)
 
 	/* Initialize SuperIO */
 	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	it8728f_b75md3v_disable_reboot(SUPERIO_GPIO);
+
+	ite_reg_write(SIO_GPIO, 0xEF, 0x7E); // magic SIO disable reboot
+
+	/* FIXME: These values could be configured in ramstage */
+	ite_reg_write(SIO_GPIO, 0x25, 0x40); // gpio pin function -> gp16
+	ite_reg_write(SIO_GPIO, 0x27, 0x10); // gpio pin function -> gp34
+	ite_reg_write(SIO_GPIO, 0x2c, 0x80); // smbus isolation on parallel port
+	ite_reg_write(SIO_GPIO, 0x62, 0x0a); // simple iobase 0xa00
+	ite_reg_write(SIO_GPIO, 0x72, 0x20); // watchdog timeout clear!
+	ite_reg_write(SIO_GPIO, 0x73, 0x00); // watchdog timeout clear!
+	ite_reg_write(SIO_GPIO, 0xcb, 0x00); // simple io set4 direction -> in
+	ite_reg_write(SIO_GPIO, 0xe9, 0x27); // bus select disable
+	ite_reg_write(SIO_GPIO, 0xf0, 0x10); // ?
+	ite_reg_write(SIO_GPIO, 0xf1, 0x42); // ?
+	ite_reg_write(SIO_GPIO, 0xf6, 0x1c); // hwmon alert beep -> gp36(pin12)
+
+	/* EC SIO settings */
+	ite_reg_write(IT8728F_EC, 0xf1, 0xc0);
+	ite_reg_write(IT8728F_EC, 0xf6, 0xf0);
+	ite_reg_write(IT8728F_EC, 0xf9, 0x48);
+	ite_reg_write(IT8728F_EC, 0x60, 0x0a);
+	ite_reg_write(IT8728F_EC, 0x61, 0x30);
+	ite_reg_write(IT8728F_EC, 0x62, 0x0a);
+	ite_reg_write(IT8728F_EC, 0x63, 0x20);
+	ite_reg_write(IT8728F_EC, 0x30, 0x01);
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
@@ -106,6 +86,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 5, 6 },
 };
 
+/* FIXME: This board only has two DIMM slots! */
 void mainboard_get_spd(spd_raw_data *spd, bool id_only) {
 	read_spd (&spd[0], 0x50, id_only);
 	read_spd (&spd[1], 0x51, id_only);