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authorKeith Hui <buurin@gmail.com>2024-02-05 16:11:26 -0500
committerMartin L Roth <gaumless@gmail.com>2024-06-07 22:39:18 +0000
commitc36b5ea18983e3dbb021ae3012698d1357dcdf66 (patch)
treef2575cdcf079c721cf89bba887cf2d28b791a256 /src/mainboard/gigabyte/ga-b75m-d3h
parent51a01bdcd65370c29342f51a29fa5741447f09dc (diff)
mb/*: Copy bd82x6x boards' USB port config into devicetree
For mainboards using southbridge/intel/bd82x6x, copy the contents of mainboard_usb_ports array into southbridge devicetree. In-line comments are maintained. Boards also capable of using MRC raminit are done in a separate patch. Change-Id: Ia8a967eb3466106f3a34e024260e13d02f449a25 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81879 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/gigabyte/ga-b75m-d3h')
-rw-r--r--src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb17
1 files changed, 16 insertions, 1 deletions
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
index 3b9584360b..81e243fd99 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
@@ -20,7 +20,22 @@ chip northbridge/intel/sandybridge
register "xhci_switchable_ports" = "0xf"
register "superspeed_capable_ports" = "0xf"
-
+ register "usb_port_config" = "{
+ { 1, 5, 0 },
+ { 1, 5, 0 },
+ { 1, 5, 1 },
+ { 1, 5, 1 },
+ { 1, 5, 2 },
+ { 1, 5, 2 },
+ { 1, 5, 3 },
+ { 1, 5, 3 },
+ { 1, 5, 4 },
+ { 1, 5, 4 },
+ { 1, 5, 6 },
+ { 1, 5, 5 },
+ { 1, 5, 5 },
+ { 1, 5, 6 }
+ }"
device ref xhci on # USB 3.0 Controller
subsystemid 0x1458 0x5007