diff options
author | Damien Zammit <damien@zamaudio.com> | 2014-11-28 15:59:10 +1100 |
---|---|---|
committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-11-30 14:56:19 +0100 |
commit | 126a2a8a78731b0f913ac0f876b4238359a483b8 (patch) | |
tree | 8d6512c4ced51b3c6037b577b70c049af809baba /src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl | |
parent | 6d0cba7978913b8f28257a0bb2e38eeb9965efc3 (diff) |
gigabyte/ga-b75m-d3h: Add new Intel mainboard
This is based on LENOVO X230 port.
Board boots to linux via SATA or USB.
All USB ports are working.
Remaining Issues:
1. Native raminit sometimes fails with "timC write discovery failed"
even without changing the ram configuration. I suggest
altering the native raminit code so that it reboots
if that message appears to give a chance for the
boot process to recover.
2. VGA does not work.
Native graphics initialization only supports LVDS and
the VGA Option ROM still hangs when run in SeaBIOS.
Change-Id: I91a7aab96d6c5f213b097cd55fcc47d4c94b3172
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7341
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl')
-rw-r--r-- | src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl new file mode 100644 index 0000000000..84a889aea7 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -0,0 +1,24 @@ +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } +} |