diff options
| author | Alex James <theracermaster@gmail.com> | 2019-05-15 20:15:47 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-16 20:19:24 +0000 |
| commit | 25b35d317eef9ef5d73bbecc502fdac13a478bf6 (patch) | |
| tree | 0f5f66b0e27ed3d396002841d5751d8e9b0395e8 /src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | |
| parent | d9391837198d838d55ecf853ca70a675f9ca36aa (diff) | |
mb/gigabyte/ga-b75m-d3{h,v}: Various cleanups
- Enable LPC TPM support in Kconfig and add pc80/tpm to devicetree
- Enable VBT support in Kconfig and add VBT files extracted from
vendor firmware
- Remove IGPU VBIOS entries from Kconfig
- Remove unused PS2 definitions in superio.asl
- Add PWRB ACPI device entry to mainboard.asl
- Remove duplicate chipset register initialization from mainboard.c
- Move ITE Super I/O configuration to mainboard_config_superio in
romstage.c
Signed-off-by: Alex James <theracermaster@gmail.com>
Change-Id: I2d11c55dc809b920bccf55f5f745d9f29b18bbb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb')
| -rw-r--r-- | src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 7a3568aba3..ceb9279365 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -21,16 +21,15 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x1458 0x5000 inherit - device pci 00.0 on # host bridge + device pci 00.0 on # Host bridge subsystemid 0x1458 0x5000 end device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on # vga controller + device pci 02.0 on # Integrated VGA controller subsystemid 0x1458 0xd000 end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - # GPI routing register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x003c0a01" @@ -109,7 +108,7 @@ chip northbridge/intel/sandybridge end chip drivers/pc80/tpm - device pnp 0c31.0 on end + device pnp 0c31.0 on end end end device pci 1f.2 on # SATA Controller 1 |