diff options
author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-11-02 22:35:28 +0100 |
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committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-11-03 00:12:52 +0100 |
commit | f94698c34ba96f336b22d3905597eb7d61c2bcdb (patch) | |
tree | 17099d578e244b45865bd7e9e96dad4f00f37c65 /src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | |
parent | 41f55b734f3eb96450c415e37e9cb1500c509e6d (diff) |
Revert "gigabyte/ga-b75m-d3h: Add new Intel mainboard"
Breaks abuild and is dependent on WIP, is WIP itself.
This reverts commit d7d0c8134854cba72f0c3fe25946b27ce0364b43.
Change-Id: I8b589b41632696aa4570abcceab5f3a3b0784649
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7319
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb')
-rw-r--r-- | src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 87 |
1 files changed, 0 insertions, 87 deletions
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb deleted file mode 100644 index bd9cdf6f1c..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ /dev/null @@ -1,87 +0,0 @@ -chip northbridge/intel/sandybridge - - # Enable DVI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - device cpu_cluster 0 on - chip cpu/intel/socket_LGA1155 - device lapic 0 on end - end - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - end - end - - device domain 0 on - subsystemid 0x1458 0x5000 inherit - device pci 00.0 on end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # vga controller - - chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - - # GPI routing - register "alt_gp_smi_en" = "0x0000" - - # Set max SATA speed to 6.0 Gb/s - register "sata_port_map" = "0x3f" - register "sata_interface_speed_support" = "0x3" - register "gen1_dec" = "0x003c0a01" - - # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" - - device pci 14.0 off end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 on end # PCI bridge (ethernet here) - device pci 1f.0 on # ISA/LPC bridge - chip superio/ite/it8728f - device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Serial Port 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 on # Environment Controller - io 0x60 = 0xa30 - io 0x62 = 0xa20 - irq 0x70 = 9 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x0 - io 0x62 = 0xa00 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.a off end # IR - end - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # SATA Controller 2 - device pci 1f.6 on end # Thermal - end - end -end - |