mb/gigabyte/ga-945gcm-s2l: add mainboard

Startpoint was Intel d945gclf, which has same chipset and
Gigabyte ga-g41m-es2l which has same Superio.

What works and is tested:
* PCI slot;
* PCIe x16 slot with GPU (RADEON HD 2600 XT) and ADD2 DVI card;
* onboard VGA output (only textmode implemented) with native graphic init;
* 533, 800, 1067MHz FSB CPU (1333MHz is unsupported by the chipset);
* serial output during and after boot.

What does not work:
* resume from suspend (does not work for d945gclf either).

Quirks:
* The Realtek ethernet card requires a reset which currently also
  hardcodes a MAC adress.

This board was only tested with the SeaBIOS payload due to flash size
constraints (512KB) and with GNU/Linux.

Change-Id: I0ff9f193105facc1b276a791790e27eb4c275085
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17033
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 53 insertions, 0 deletions

diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl
new file mode 100644
index 0000000000..187481a1e2
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20090419	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+
+	// General Purpose Events
+	//#include "acpi/gpe.asl"
+
+	// mainboard specific devices
+	#include "acpi/mainboard.asl"
+
+	// Thermal Zone
+	//#include "acpi/thermal.asl"
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/i945/acpi/i945.asl>
+			#include <southbridge/intel/i82801gx/acpi/ich7.asl>
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}