diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-10-20 09:19:07 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-22 02:17:24 +0000 |
| commit | c85890d0d8887462e72837c3ae6dd5b6842a81cb (patch) | |
| tree | 3ccbe8cd45e134361b5dd1661c6bdd76230efd95 /src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout | |
| parent | fea2429e254c41b192dd0856966d5f80eb15a07a (diff) | |
soc/intel/cannonlake: Change max root port to 16
Cannonlake SOC support up to 16 PCI express root port.
BUG=CID 1381813;1381814;
Change-Id: I4df610e3fb01bd8e62be7e9c62144125f2a96c25
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout')
0 files changed, 0 insertions, 0 deletions