diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-28 13:27:52 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-04 08:59:41 +0000 |
| commit | b262293607fa383bd90e68aa38d13e676ba4a014 (patch) | |
| tree | b900dec4bbd605534d2c1774aec47ea00678980e /src/mainboard/getac/p470/devicetree.cb | |
| parent | 39a18093494eeab31f2d1b6eedff86b19accdf5c (diff) | |
mb/getac: Get rid of whitespace before tab
Change-Id: Ib7068f381971d1270b22cb03937f1e7fa30acb46
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/getac/p470/devicetree.cb')
| -rw-r--r-- | src/mainboard/getac/p470/devicetree.cb | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 415d9a3945..ad3b625a76 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -63,19 +63,19 @@ chip northbridge/intel/i945 register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe port 1 - device pci 1c.1 on end # PCIe port 2 - device pci 1c.2 on end # PCIe port 3 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe port 1 + device pci 1c.1 on end # PCIe port 2 + device pci 1c.2 on end # PCIe port 3 device pci 1c.3 on end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on chip southbridge/ti/pcixx12 end |