Add support for the Getac P470

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

10 files changed, 2333 insertions, 0 deletions

diff --git a/src/mainboard/getac/p470/acpi/battery.asl b/src/mainboard/getac/p470/acpi/battery.asl
new file mode 100644
index 0000000000..8a69a8815b
--- /dev/null
+++ b/src/mainboard/getac/p470/acpi/battery.asl
@@ -0,0 +1,262 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope(\_SB) {
+
+	Name(NIMH, "NiMH")
+	Name(LION, "Lion")
+
+	Device (BAT0)
+	{
+		Name(_HID, EisaId("PNP0C0A"))
+		Name(_UID, 1)
+
+		Name(_PCL, Package(){ \_SB })
+
+		Name(PBST, Package() { 0x00, 0x04b0, 0x0bb8, 0x03e8 })
+
+		/* Status */
+		Method(_STA, 0)
+		{
+			Sleep(120)
+			If(\_SB.PCI0.LPCB.EC0.BAT) {
+				Return(0x1f)
+			} Else {
+				Return(0x0f)
+			}
+		}
+
+		/* Battery Info */
+		Method(_BIF, 0)
+		{
+			Name(PBIF, Package() {
+				0x01,
+				0x0fa0,
+				0x0fa0,
+				0x01,
+				0x2ee0,	// Capacity?
+				0x012c,
+				0x96,
+				0x01,
+				0x01,
+				"Battery",	// Name
+				"",		// Number
+				"LIon",		// Type
+				"Generic"	// Vendor
+			})
+
+			// Is battery there?
+			Store(_STA(), Local0)
+			And(Local0, 0x10, Local0)
+			If(LNot(Local0)) {
+				Return (PBIF)
+			}
+
+			Store(\_SB.PCI0.LPCB.EC0.BDC0, Index(PBIF, 1))
+			Store(\_SB.PCI0.LPCB.EC0.BDV0, Index(PBIF, 4))
+
+			Store(\_SB.PCI0.LPCB.EC0.BFC0, Local0)
+			Store(Local0, Index(PBIF, 2))
+
+			Divide(Local0, 10, Local1, Local2)
+			Store(Local2, Index(PBIF, 5))
+
+			Divide(Local0, 20, Local1, Local2)
+			Store(Local2, Index(PBIF, 6))
+
+			If(\_SB.PCI0.LPCB.EC0.BTYP) {
+				Store(NIMH, Index(PBIF, 11))
+			} Else {
+				Store(LION, Index(PBIF, 11))
+			}
+
+			Return(PBIF)
+		}
+
+		/* Battery Status */
+		Method(_BST, 0)
+		{
+			If(\_SB.PCI0.LPCB.EC0.BAT) {
+				Store(\_SB.PCI0.LPCB.EC0.BPV0, Index(PBST, 3))
+
+				Multiply(\_SB.PCI0.LPCB.EC0.BRC0, 100, Local3)
+				Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC0, Local3, Local0)
+				Multiply(\_SB.PCI0.LPCB.EC0.BFC0, Local0, Local3)
+				Divide(Local3, 0x64, Local3, Local0)
+				Increment(Local0)
+				Store(Local0, Index(PBST, 2))
+
+				Store (\_SB.PCI0.LPCB.EC0.BRC0, Local3)
+				Store (\_SB.PCI0.LPCB.EC0.BPR0, Local0)
+				And (Not (Local0), 0xFFFF, Local0)
+				Store (Local0, Index(PBST,1))
+
+				// AC Power connected?
+				If(\_SB.PCI0.LPCB.EC0.ADP) {
+					If(\_SB.PCI0.LPCB.EC0.CHRG) {
+						Store(2, Index(PBST, 0))
+					} Else {
+						Store(0, Index(PBST, 0))
+					}
+				} Else {
+					If(LLess(Local3, 25)) {
+						Store(5, Index(PBST, 0))
+					} Else {
+						Store(1, Index(PBST, 0))
+					}
+				}
+			}
+			Return(PBST)
+		}
+	}
+
+
+	Device (BAT1)
+	{
+		Name(_HID, EisaId("PNP0C0A"))
+		Name(_UID, 1)
+
+		Name(_PCL, Package(){ \_SB })
+
+		Name(PBST, Package() { 0x00, 0x04b0, 0x0bb8, 0x03e8 })
+
+		/* Status */
+		Method(_STA, 0)
+		{
+			Sleep(120)
+			If(\_SB.PCI0.LPCB.EC0.BAT2) {
+				Return(0x1f)
+			} Else {
+				Return(0x0f)
+			}
+		}
+
+		/* Battery Info */
+		Method(_BIF, 0)
+		{
+			Name(PBIF, Package() {
+				0x01,
+				0x0fa0,
+				0x0fa0,
+				0x01,
+				0x2ee0,	// Capacity?
+				0x012c,
+				0x96,
+				0x01,
+				0x01,
+				"Battery",	// Name
+				"",		// Number
+				"LIon",		// Type
+				"Generic"	// Vendor
+			})
+
+			// Is battery there?
+			Store(_STA(), Local0)
+			And(Local0, 0x10, Local0)
+			If(LNot(Local0)) {
+				Return (PBIF)
+			}
+
+			Store(\_SB.PCI0.LPCB.EC0.BDC2, Index(PBIF, 1))
+			Store(\_SB.PCI0.LPCB.EC0.BDV2, Index(PBIF, 4))
+
+			Store(\_SB.PCI0.LPCB.EC0.BFC2, Local0)
+			Store(Local0, Index(PBIF, 2))
+
+			Divide(Local0, 10, Local1, Local2)
+			Store(Local2, Index(PBIF, 5))
+
+			Divide(Local0, 20, Local1, Local2)
+			Store(Local2, Index(PBIF, 6))
+
+			If(\_SB.PCI0.LPCB.EC0.BTY2) {
+				Store(NIMH, Index(PBIF, 11))
+			} Else {
+				Store(LION, Index(PBIF, 11))
+			}
+
+			Return(PBIF)
+		}
+
+		/* Battery Status */
+		Method(_BST, 0)
+		{
+			If(\_SB.PCI0.LPCB.EC0.BAT2) {
+				Store(\_SB.PCI0.LPCB.EC0.BPV2, Index(PBST, 3))
+
+				Multiply(\_SB.PCI0.LPCB.EC0.BRC2, 100, Local3)
+				Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC2, Local3, Local0)
+				Multiply(\_SB.PCI0.LPCB.EC0.BFC2, Local0, Local3)
+				Divide(Local3, 0x64, Local3, Local0)
+				Increment(Local0)
+				Store(Local0, Index(PBST, 2))
+
+				Store (\_SB.PCI0.LPCB.EC0.BRC2, Local3)
+				Store (\_SB.PCI0.LPCB.EC0.BPR2, Local0)
+				And (Not (Local0), 0xFFFF, Local0)
+				Store (Local0, Index(PBST,1))
+
+				// AC Power connected?
+				If(\_SB.PCI0.LPCB.EC0.ADP) {
+					If(\_SB.PCI0.LPCB.EC0.CRG2) {
+						Store(2, Index(PBST, 0))
+					} Else {
+						Store(0, Index(PBST, 0))
+					}
+				} Else {
+					If(LLess(Local3, 25)) {
+						Store(5, Index(PBST, 0))
+					} Else {
+						Store(1, Index(PBST, 0))
+					}
+				}
+			}
+			Return(PBST)
+		}
+	}
+
+	Name (PWRS, 0)
+	Name (ACFG, 0)
+
+	Device (AC)
+	{
+		Name (_HID, "ACPI0003")
+		Name (ACST, 0x00)
+		Method (_PSR, 0)
+		{
+			If(ACFG) {
+				Store(ACST, Local0)
+			} Else {
+				Store(\_SB.PCI0.LPCB.EC0.ADP, Local0)
+				Store(Local0, ACST)
+				Store(1, ACFG)
+			}
+			Sleep(120)
+			Return (Local0)
+		}
+
+		Name(_PCL, Package(){
+			\_SB,
+			BAT0,
+			BAT1
+		})
+	}
+}
diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl
new file mode 100644
index 0000000000..30e78fad2a
--- /dev/null
+++ b/src/mainboard/getac/p470/acpi/ec.asl
@@ -0,0 +1,675 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device(EC0)
+{
+	Name (_HID, EISAID("PNP0C09"))
+	Name (_UID, 1)
+
+	Name (_GPE, 23)	// GPI07 / GPE23 -> Runtime SCI
+
+	OperationRegion(ERAM, EmbeddedControl, 0x00, 0x37)
+	Field (ERAM, ByteAcc, NoLock, Preserve)
+	{
+		MODE,	  1,	// Thermal Policy (Quiet/Perform)
+		FAN,	  1,	// Fan Power (On/Off)
+		LIDS, 	  1,	// LID Status (0=Open/1=Close)
+		LSW0,	  1,	// LCD Power Switch
+
+		BTYP,	  1,	// Battery Type (0=LiIon/1=NiMh)
+		MWKE,	  1,	// Enable Wakeup from RI
+		ADP,	  1,	// AC Adapter (0=Offline/1=Online)
+		BAT,	  1,	// Battery (0=Not Present/1=Present)
+		SLPT,	  3,	// Set Sleep Type on SLP enter (1=S1...4=S4)
+		CHRG,	  1,	// 0=Battery not charging/1=Battery charging
+		RI_W,	  1,	// Wake-up event source is RI
+		KB_W,	  1,	// Wake-up event source is keyboard
+		BATW,	  1,	// Wake-up event source is Battery Low
+		PMEW,	  1,	// Wake-up event source is PME
+
+		// Battery 0 Registers
+		// Battery Life = BRC0/BPR0
+		// Battery percentage = BRC0/BFC0 * 100
+		BDC0,	 16,	// Designed Capacity
+		BFC0,	 16,	// Last Full Charge Capacity
+		BDV0,	 16,	// Design Voltage
+		BPR0,	 16,	// Battery Present Rate
+		BRC0,	 16,	// Battery Remaining Capacity
+		BPV0,	 16,	// Battery Present Voltage
+
+		Offset(0x11),
+		CTMP,	  8,	// CPU Temperature
+		Offset(0x15),
+		CTRO,	  8,	// EC throttling on trip point
+		CRTT,	  8,	// Critical Shut-down Temperature
+		Offset(0x17),
+		BKLL,	  8,	// Backlight Level
+
+		// Battery 2 Registers
+		Offset(0x20),
+		,	  4,
+		BTY2,	  1,	// Battery Type (0=LiIon/1=NiMh)
+		,	  2,
+		BAT2,	  1,	// Battery (0=Not Present/1=Present)
+		,	  3,
+		CRG2,	  1,	// 0=Battery not charging/1=Battery charging
+		Offset(0x22),
+		BDC2,	 16,	// Designed Capacity
+		BFC2,	 16,	// Last Full Charge Capacity
+		BDV2,	 16,	// Design Voltage
+		BPR2,	 16,	// Battery Present Rate
+		BRC2,	 16,	// Battery Remaining Capacity
+		BPV2,	 16,	// Battery Present Voltage
+		BTP2,	 16,	// Trip Point
+
+		PBMO,	  2,	// PBMO power control method
+		ECO,	  1,	// ECO on/off status
+		SUN,	  1,	// Sunlight Readable
+		RF,	  1,	// RF Enable/Disable status
+		DOCK,	  1,	// Dock In/Out status
+		CBAT,	  1,	// Car Battery status
+		APPS,	  1,	// OSD utility status
+		Offset(0x33),
+		ODDS,	  1
+	}
+
+	Method (_CRS, 0)
+	{
+		Name (ECMD, ResourceTemplate()
+		{
+			IO (Decode16, 0x62, 0x62, 1, 1)
+			IO (Decode16, 0x66, 0x66, 1, 1)
+		})
+
+		Return (ECMD)
+	}
+
+	// EC Query methods, called upon SCI interrupts.
+	Method (_Q01, 0)
+	{
+		Notify (\_PR.CPU0, 0x80)
+		If(ADP) {
+			Store(1, \_SB.AC.ACST)
+			TRAP(0xe3)
+			Store(1, PWRS)
+			TRAP(0x2b)
+		} Else {
+			Store(0, \_SB.AC.ACST)
+			Notify(\_SB.AC, 0x80)
+			Notify(\_SB.BAT0, 0x80)
+			Store(0, PWRS)
+			TRAP(0x2b)
+		}
+
+		PNOT()
+	}
+
+	Method (_Q02, 0)
+	{
+		If(BAT) {
+			Notify(\_SB.BAT0, 0x00)
+			Notify(\_SB.AC, 0x80)
+		} Else {
+			Notify(\_SB.AC, 0x80)
+			Notify(\_SB.BAT0, 0x01)
+		}
+
+		PNOT()
+	}
+
+	Method (_Q05, 0)
+	{
+		Notify(SLPB, 0x80)
+		PNOT()
+	}
+
+	Method (_Q07, 0)
+	{
+		TRAP(0xe0)
+
+		If (LEqual(RTCF, 0x00)) {
+			Notify(LID0, 0x80)
+		} else {
+			TRAP(0xc1)
+		}
+	}
+	
+	Method (_Q09, 0)
+	{
+		Notify(BAT0, 0x80)
+		Notify(BAT1, 0x80)
+	}
+
+	Method (_Q0A, 0)
+	{
+		Notify(\_TZ.THRM, 0x80)
+	}
+	
+	Method (_Q20, 0)
+	{
+		Notify(\_SB.ECO, 0x81)
+	}
+
+	Method (_Q21, 0)
+	{
+		Notify(\_SB.ECO, 0x82)
+	}
+
+	Method (_Q22, 0)
+	{
+		Notify(\_SB.ECO, 0x83)
+	}
+
+	Method (_Q23, 0)
+	{
+		Notify(\_SB.ECO, 0x84)
+	}
+
+	Method (_Q24, 0)
+	{
+		Store(0x3f, HOTK)
+		If(IGDS) {
+			HKDS(10)
+		} Else {
+			TRAP(0xE1)
+		}
+		Notify (\_SB.ECO, 0x85)
+	}
+
+	Method (_Q25, 0)
+	{
+		Store(0x40, HOTK)
+		TRAP(0xe1)
+		Notify(\_SB.ECO, 0x86)
+	}
+
+	Method (_Q26, 0)
+	{
+		Store(0x41, HOTK)
+		TRAP(0xe1)
+		Notify(\_SB.ECO, 0x87)
+	}
+
+	Method (_Q27, 0)
+	{
+		Notify(\_SB.ECO, 0x88)
+	}
+
+	Method (_Q28, 0)
+	{
+		Notify(\_SB.ECO, 0x89)
+	}
+
+	Method (_Q29, 0)
+	{
+		Notify(\_SB.ECO, 0x8a)
+	}
+
+	Method (_Q2A, 0)
+	{
+		Store(0x57, HOTK)
+		TRAP(0xe1)
+		Notify(\_SB.ECO, 0x8b)
+	}
+
+	Method (_Q2B, 0)
+	{
+		Notify(SLPB, 0x80)
+		Notify(\_SB.ECO, 0x8c)
+	}
+
+	Method (_Q2C, 0)
+	{
+		Store(0x59, HOTK)
+		TRAP(0xe1)
+	}
+
+	Method (_Q38, 0)
+	{
+		// IDE TODO
+	}
+
+	Method (_Q39, 0)
+	{
+		// SATA TODO
+	}
+
+	Method (_Q3A, 0)
+	{
+		Store(1, BRTL)
+		Notify(\_SB.ECO, 0x93)
+	}
+
+	Method (_Q3B, 0)
+	{
+		Store(0, BRTL)
+		Notify(\_SB.ECO, 0x93)
+	}
+
+	Method (_Q3C, 0)
+	{
+		Store(1, SUN)
+		Notify(\_SB.ECO, 0x92)
+	}
+
+	Method (_Q3D, 0)
+	{
+		Store(0, SUN)
+		Notify(\_SB.ECO, 0x92)
+	}
+
+	/* Enable RF device */
+	Method (_Q3E, 0)
+	{
+		TRAP(0xdf)
+	}
+
+	/* Disable RF device */
+	Method (_Q3F, 0)
+	{
+		TRAP(0xc0)
+	}
+
+	/* ACBS LAN Power On */
+	Method (_Q40, 0)
+	{
+		TRAP(0xd0)
+		Sleep(500)
+		Notify(RP04, 0)
+	}
+
+	/* ACBS LAN Power Off */
+	Method (_Q41, 0)
+	{
+		TRAP(0xd1)
+	}
+
+	Method (_Q42, 0)
+	{
+		TRAP(0xf3)
+	}
+
+	Method (_Q43, 0)
+	{
+		TRAP(0xf4)
+	}
+
+	Method (_Q48, 0)
+	{
+		TRAP(0xd2) // Check AC Status
+		Store (1, ODDS)
+		Notify(\_SB.ECO, 0x90)
+	}
+
+	Method (_Q49, 0)
+	{
+		TRAP(0xd2) // Check AC Status
+		Store (0, ODDS)
+		Notify(\_SB.ECO, 0x90)
+	}
+
+
+	Method (_Q4C, 0)
+	{
+		Notify(\_SB.ECO, 0x94)
+	}
+
+	Method (_Q4D, 0)
+	{
+		Notify(\_SB.ECO, 0x95)
+	}
+
+	Method (_Q4E, 0)
+	{
+		// PATA TODO
+	}
+
+	Method (_Q4F, 0)
+	{
+		TRAP(0xf9)
+		Notify(\_SB.ECO, 0x95)
+	}
+
+	Method (_Q5C, 0)
+	{
+		// Store(2, IGPS)
+		Notify(\_SB.ECO, 0x94)
+	}
+
+	Method (_Q70, 0)
+	{
+		Notify(\_SB.ECO, 0x96)
+	}
+
+	Method (_Q71, 0)
+	{
+		Notify(\_SB.ECO, 0x97)
+	}
+
+	// TODO Scope _SB devices for AC power, LID, Power button
+}
+
+Scope(\_SB)
+{
+	/* This device is used by the GETAC P470 Windows drivers. */
+
+	Device (ECO)
+	{
+		Name(_HID, "MTC0303") // MTC0303 BIOS Service Provider
+		Method (GDPD, 0, Serialized)
+		{
+			// Set flag byte to zero
+			Store (0, Local0)
+
+			If (And(BRTL, 0x01)) {
+				Or(Local0, 0x01, Local0)
+			}
+
+			If (And(BRTL, 0x02)) {
+				Or(Local0, 0x04, Local0)
+			}
+
+			If (And(BRTL, 0x04)) {
+				Or(Local0, 0x02, Local0)
+			}
+
+			If (And(BRTL, 0x30)) {
+				Or(Local0, 0x10, Local0)
+			}
+
+			If (And(BRTL, 0x40)) {
+				Or(Local0, 0x40, Local0)
+			}
+
+			Return (Local0)
+		}
+
+		Method (GDPC, 0, Serialized)
+		{
+			Store (0, Local0)
+
+			If (And(BRTL, 0x10)) {
+				Or(Local0, 0x04, Local0)
+			}
+
+			If (And( BRTL, 0x20)) {
+				Or(Local0, 0x01, Local0)
+			}
+
+			If (And(BRTL, 0x40)) {
+				Or(Local0, 0x02, Local0)
+			}
+
+			Return (Local0)
+		}
+
+		/* Set Brightness Level */
+		Method(SBLL, 1, Serialized)
+		{
+			Store (Arg0, BRTL)
+			TRAP(0xd5)	// See mainboard_smi.c
+			Return (0)
+		}
+
+		/* Get Brightness Level */
+		Method(GBLL, 0, Serialized)
+		{
+			TRAP(0xd6)	// See mainboard_smi.c
+			Return (BRTL)
+		}
+
+		/* Get Brightness Level Medium? */
+		Method(GBLM, 0, Serialized)
+		{
+			Store(0x3f, BRTL)
+			// XXX don't we have to set the brightness?
+			Return(BRTL)
+		}
+
+		/* ??? */
+		Method(SUTE, 1, Serialized)
+		{
+			If (And(Arg0, 0x01)) {
+				TRAP(0xf5)
+			} Else {
+				TRAP(0xf6)
+			}
+			Return (0)
+		}
+
+		/* ??? */
+		Method(GECO, 0, Serialized)
+		{
+			TRAP(0xd7)
+			Return (ODDS)
+		}
+
+		/* ??? */
+		Method(GBSL, 0, Serialized)
+		{
+			TRAP(0xd8)
+			Return (BRTL)
+		}
+
+		/* ??? Get LED/Device Enable Status */
+		Method(GRFD, 0, Serialized)
+		{
+			/* Let coreboot update the flags */
+			TRAP(0xe5)
+
+			Store (0, Local0)
+			If(And(RFDV, 0x01)) {
+				Or(Local0, 0x01, Local0)
+			}
+			If(And(RFDV, 0x02)) {
+				Or(Local0, 0x02, Local0)
+			}
+			If(And(RFDV, 0x02)) {
+				Or(Local0, 0x02, Local0)
+			}
+			If(And(RFDV, 0x04)) {
+				Or(Local0, 0x04, Local0)
+			}
+			If(And(RFDV, 0x08)) {
+				Or(Local0, 0x08, Local0)
+			}
+			If(And(GP16, 0x01)) {		// GDIS
+				Or(Local0, 0x10, Local0)
+			}
+			If(And(GP13, 0x01)) {		// WIFI Led (WLED)
+				Or(Local0, 0x20, Local0)
+			}
+			If(And(BTEN, 0x01)) {		// BlueTooth Enable
+				Or(Local0, 0x40, Local0)
+			}
+			If(And(GP11, 0x01)) {		// GPS Enable
+				Or(Local0, 0x80, Local0)
+			}
+
+			Return (Local0)
+		}
+
+		/* Set RFD */
+		Method(SRFD, 1, Serialized)
+		{
+			If (And(Arg0, 0x01)) {
+				Store (1, GP15)		// GLED
+				Store (1, GP16)		// GDIS
+			} Else {
+				Store (0, GP15)
+				Store (0, GP16)
+			}
+
+			/* WIFI */
+			If (And(Arg0, 0x02)) {
+				Store (1, GP13)		// WLED
+				Store (1, GP26)		// WLAN
+			} Else {
+				Store (0, GP13)
+				Store (0, GP26)
+			}
+
+			/* Bluetooth */
+			If (And(Arg0, 0x04)) {
+				Store (1, GP14)		// BLED
+				Store (1, BTEN)
+			} Else {
+				Store (0, GP14)		// BLED
+				Store (0, BTEN)
+			}
+			Return (0)
+		}
+
+		/* Get DKD */
+		Method(GDKD, 0, Serialized)
+		{
+			TRAP(0xd9)
+			Return (BRTL)
+		}
+
+		/* Set DKD */
+		Method(SDKD, 1, Serialized)
+		{
+			TRAP(0xda)
+			Return (0)
+		}
+
+		/* Set IGD (Graphics) */
+		Method(SIGD, 1, Serialized)
+		{
+			If (And(Arg0, 0x01)) {
+				TRAP(0xf7)
+			} Else {
+				TRAP(0xf8)
+			}
+			Return (0)
+		}
+
+		/* SMI-C? Set Mic? */
+		Method (SMIC, 1, Serialized)
+		{
+			If (And(Arg0, 0x01)) {
+				TRAP(0xeb)
+			} Else {
+				TRAP(0xec)
+			}
+			Return (0)
+		}
+
+		/* ??? */
+		Method(GTSD, 0, Serialized)
+		{
+			Return (GP20)	// TSDT
+		}
+
+		/* Not even decent function names anymore? */
+		Method(S024, 1, Serialized)
+		{
+			If (And(Arg0, 0x01)) {
+				TRAP(0xf1)
+			} Else {
+				TRAP(0xf2)
+			}
+			Return (0)
+		}
+
+		/* Get CVD */
+		Method(GCVD, 0, Serialized)
+		{
+			TRAP(0xf9)
+			Return (BRTL)
+		}
+
+		/* ??? Something with PATA */
+		Method(S025, 1, Serialized)
+		{
+			If(And(Arg0, 0x01)) {
+				TRAP(0xfc)
+
+				Store (1, GP33)		// CREN
+				Sleep(1500)
+
+				Store (1, GP34)		// CRRS
+				Sleep(500)
+
+				Notify(^^PCI0.PATA, 0)
+				Notify(^^PCI0.PATA.PRID, 0)
+			} Else {
+				TRAP(0xfb)
+				Sleep(1500)
+				Store(0, GP33)		// CREN
+				Sleep(1500)
+				Notify(^^PCI0.PATA, 0)
+				Notify(^^PCI0.PATA.PRID, 0)
+				Notify(^^PCI0.PATA.PRID.DSK1, 1)
+				Notify(^^PCI0.PATA.PRID.DSK0, 1)
+			}
+			Return (0)
+		}
+
+		/* ??? */
+		Method(G021, 0, Serialized)
+		{
+			TRAP(0xfe)
+			If (LEqual(ACIN, 0)) {
+				TRAP(0xfa)
+				TRAP(0xfd)
+				If (LEqual(ODDS, 1)) {
+					TRAP(0xfb)
+					Notify(^^PCI0.PATA, 0)
+					Notify(^^PCI0.PATA.PRID.DSK1, 1)
+					Notify(^^PCI0.PATA.PRID.DSK0, 1)
+					Sleep (1500)
+					Store (0, GP33)		// CREN
+					Sleep (1500)
+					Notify(^^PCI0.PATA, 0)
+					Notify(^^PCI0.PATA.PRID.DSK1, 1)
+					Notify(^^PCI0.PATA.PRID.DSK0, 1)
+					Return (0)
+				}
+			}
+			/* All Else Cases */
+			Notify(ECO, 0xb1)
+			Return (1)
+		}
+
+		/* Get RFS */
+		Method(GRFS, 0, Serialized)
+		{
+			TRAP(0xff)
+			Return(BRTL)
+		}
+
+		/* ??? */
+		Method(S00B, 1, Serialized)
+		{
+			If (And(Arg0, 1)) {
+				TRAP(0xdc)
+			} Else {
+				TRAP(0xdd)
+			}
+			Return (0)
+		}
+		
+	
+
+	}
+}
diff --git a/src/mainboard/getac/p470/acpi/gpe.asl b/src/mainboard/getac/p470/acpi/gpe.asl
new file mode 100644
index 0000000000..7dc18c8211
--- /dev/null
+++ b/src/mainboard/getac/p470/acpi/gpe.asl
@@ -0,0 +1,104 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (_GPE)
+{
+	/* The event numbers correspond to the bit numbers in the
+	 * GPE0_EN register PMBASE + 0x2C.
+	 */
+
+	// Hot Plug
+	Method (_L01, 0)
+	{
+		// TODO
+	}
+
+	// Software GPE
+	Method (_L02, 0)
+	{
+		Store (0, GPEC)
+	}
+
+	// USB1
+	Method (_L03, 0)
+	{
+		Notify (\_SB.PCI0.USB1, 2)
+	}
+
+	// USB2
+	Method (_L04, 0)
+	{
+		Notify (\_SB.PCI0.USB2, 2)
+	}
+
+	// AC97
+	Method (_L05, 0)
+	{
+		Notify (\_SB.PCI0.MODM, 2)
+		Notify (\_SB.PCI0.HDEF, 2)
+	}
+
+	// _L06 TCOSCI
+
+	// SMBus (Reserved!)
+	Method (_L07, 0)
+	{
+		Store (0x20, \_SB.PCI0.SBUS.HSTS)
+	}
+
+	// COM1/COM2 (RI)
+	Method (_L08, 0)
+	{
+		// Don't care
+	}
+
+	// PCIe
+	Method (_L09, 0)
+	{
+		// TODO
+	}
+
+	// _L0A BatLow / Quick Resume
+
+	// PME
+	Method (_L0B, 0)
+	{
+		Notify (\_SB.PCI0.PCIB.LANR, 0x02)
+	}
+
+	// USB3
+	Method (_L0C, 0)
+	{
+		Notify(\_SB.PCI0.USB3, 2)
+	}
+
+	// PME B0
+	Method (_L0D, 0)
+	{
+		Notify(\_SB.PCI0.EHC1, 2)
+	}
+
+	// USB4
+	Method (_L0E, 0)
+	{
+		Notify(\_SB.PCI0.USB4, 2)
+	}
+}
diff --git a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl b/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl
new file mode 100644
index 0000000000..c78d7d6248
--- /dev/null
+++ b/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the 
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// PCIe Graphics		0:1.0
+			Package() { 0x0001ffff, 0, 0, 16 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// Network
+			Package() { 0x0007ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },
+			Package() { 0x001cffff, 1, 0, 16 },
+			Package() { 0x001cffff, 2, 0, 18 },
+			Package() { 0x001cffff, 3, 0, 19 },
+			// USB and EHCI			0:1d.x
+			Package() { 0x001dffff, 0, 0, 23 },
+			Package() { 0x001dffff, 1, 0, 19 },
+			Package() { 0x001dffff, 2, 0, 18 },
+			Package() { 0x001dffff, 3, 0, 16 },
+			// AC97				0:1e.2, 0:1e.3
+			Package() { 0x001effff, 0, 0, 22 },
+			Package() { 0x001effff, 1, 0, 20 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, 0, 18 },
+			Package() { 0x001fffff, 1, 0, 19 },
+			Package() { 0x001fffff, 3, 0, 16 }
+		})
+	} Else {
+		Return (Package() {
+			// PCIe Graphics		0:1.0
+			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// Network			0:7.0
+			Package() { 0x0007ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			// USB and EHCI			0:1d.x
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+			// AC97				0:1e.2, 0:1e.3
+			Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
+		})
+	}
+}
+
diff --git a/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl b/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000000..28b06a1e3e
--- /dev/null
+++ b/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the 
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+	Return (Package() {
+		Package() { 0x0005ffff, 0, 0, 16},
+		Package() { 0x0005ffff, 1, 0, 17},
+		Package() { 0x0005ffff, 2, 0, 18},
+		Package() { 0x0005ffff, 4, 0, 19} // ?? 4 ??
+	})
+} Else {
+	Return (Package() {
+		Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0005ffff, 4, \_SB.PCI0.LPCB.LNKD, 0}, // Really 4??
+	})
+}
+
diff --git a/src/mainboard/getac/p470/acpi/mainboard.asl b/src/mainboard/getac/p470/acpi/mainboard.asl
new file mode 100644
index 0000000000..88ff8b4ea7
--- /dev/null
+++ b/src/mainboard/getac/p470/acpi/mainboard.asl
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (LID0)
+{
+	Name(_HID, EisaId("PNP0C0D"))
+	Method(_LID, 0)
+	{
+		If(\_SB.PCI0.LPCB.EC0.LIDS) {
+			Return (0)
+		} Else {
+			Return (1)
+		}
+	}
+}
+
+Device (SLPB)
+{
+	Name(_HID, EisaId("PNP0C0E"))
+}
+
+Device (PWRB)
+{
+	Name(_HID, EisaId("PNP0C0C"))
+	
+	// Wake
+	Name(_PRW, Package(){0x1d, 0x04})
+}
+
+#include "acpi/battery.asl"
diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl
new file mode 100644
index 0000000000..eeaded838f
--- /dev/null
+++ b/src/mainboard/getac/p470/acpi/platform.asl
@@ -0,0 +1,287 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* SMI Function Trap */
+OperationRegion(SMI1, SystemMemory, 0xC0DEDEAD, 0x100)
+Field(SMI1, AnyAcc, NoLock, Preserve)
+{
+	BCMD,  8,
+	DID,  32,
+	INFO, 1024
+}
+
+/* The _PIC method is called by the OS to choose between interrupt 
+ * routing via the i8259 interrupt controller or the APIC.
+ * 
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	TRAP(0xed)
+	Sleep(1000)
+
+	Store(0, \_SB.ACFG)
+
+	// Are we going to S3?
+	If (LEqual(Arg0, 3)) {
+		Store (0x4c, BCMD)
+	}
+
+	// Are we going to S4?
+	If (Lequal(Arg0, 4)) {
+		TRAP(0xe7)
+		TRAP(0xea)
+	}
+
+	// Are we going to S5?
+	If (Lequal(Arg0, 5)) {
+		Store (0x4b, BCMD)
+		TRAP(0xde)
+	}
+
+	// The 2.6.12.5 ACPI engine seems to optimize the
+	// If(LEqual(Arg0, 5)) path away. This keeps it from doing so:
+	TRAP(Arg0)
+	Store(Arg0, DBG0)
+	// End of ugly OS bug workaround
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	// Enable GPS
+	Store (1, GP11) // GPSE
+
+	// Wake from S3 or S4?
+	If (LOr(LEqual(Arg0, 3), LEqual(Arg0, 4))) {
+		If (And(CFGD, 0x01000000)) {
+			If (LAnd(And(CFGD, 0xf0), LEqual(OSYS, 2001))) {
+				TRAP(0x3d)
+			}
+		}
+	}
+
+	// Notify PCI Express slots in case a card
+	// was inserted while a sleep state was active.
+	
+	If (LEqual(RP1D, 0)) {
+		Notify(\_SB.PCI0.RP01, 0)
+	}
+
+	If (LEqual(RP3D, 0)) {
+		Notify(\_SB.PCI0.RP03, 0)
+	}
+
+	If (LEqual(RP4D, 0)) {
+		Notify(\_SB.PCI0.RP04, 0)
+	}
+
+	// Are we coming from S3? 
+	If (LEqual(Arg0, 3)) {
+		TRAP(0xeb)
+		TRAP(0x46)
+	}
+
+	// Are we coming from S4? 
+	If (LEqual(Arg0, 4)) {
+		Notify(SLPB, 0x02)
+		If (DTSE) {
+			TRAP(0x47)
+		}
+	}
+
+	// Windows XP SP2 P-State restore
+	If (LAnd(LEqual(OSYS, 2002), And(CFGD, 1))) {
+		If (LGreater(\_PR.CPU0._PPC, 0)) {
+			Subtract(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC)
+			PNOT()
+			Add(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC)
+			PNOT()
+		} Else {
+			Add(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC)
+			PNOT()
+			Subtract(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC)
+			PNOT()
+		}
+	}
+
+	Return(Package(){0,0})
+}
+
+// Power notification
+
+External (\_PR_.CPU0, DeviceObj)
+External (\_PR_.CPU1, DeviceObj)
+External (\_PR_.CPU0._PPC)
+External (\_PR_.CPU1._PPC)
+/* These come from the dynamically created CPU SSDT */
+External(PDC0)
+External(PDC1)
+
+Method (PNOT)
+{
+	If (MPEN) {
+		If(And(PDC0, 0x08)) {
+			Notify (\_PR_.CPU0, 0x80)	 // _PPC
+
+			If (And(PDC0, 0x10)) {
+				Sleep(100)
+				Notify(\_PR_.CPU0, 0x81) // _CST
+			}
+		}
+
+		If(And(PDC1, 0x08)) {
+			Notify (\_PR_.CPU1, 0x80)	 // _PPC
+			If (And(PDC1, 0x10)) {
+				Sleep(100)
+				Notify(\_PR_.CPU1, 0x81) // _CST
+			}
+		}
+
+	} Else { // UP
+		Notify (\_PR_.CPU0, 0x80)
+		Sleep(0x64)
+		Notify(\_PR_.CPU0, 0x81)
+	}
+
+	// Notify the Batteries
+	Notify(\_SB.BAT0, 0x80) // Execute BAT0 _BST
+	Notify(\_SB.BAT1, 0x80) // Execute BAT1 _BST
+}
+
+// Hardcoded for now..
+Name (CFGD, 0x113B69F1)
+
+/* System Bus */
+
+Scope(\_SB)
+{
+	/* This method is placed on the top level, so we can make sure it's the
+	 * first executed _INI method.
+	 */
+	Method(_INI, 0)
+	{
+		/* The DTS data in NVS is probably not up to date.
+		 * Update temperature values and make sure AP thermal
+		 * interrupts can happen
+		 */
+		If (DTSE) {
+			TRAP(0x47)
+		}
+
+		/* Determine the Operating System and save the value in OSYS.
+		 * We have to do this in order to be able to work around
+		 * certain windows bugs.
+		 *
+		 *    OSYS value | Operating System
+		 *    -----------+------------------
+		 *       2000    | Windows 2000
+		 *       2001    | Windows XP(+SP1)
+		 *       2002    | Windows XP SP2
+		 *       2006    | Windows Vista
+		 *       ????    | Windows 7
+		 */
+
+		/* Let's assume we're running at least Windows 2000 */
+		Store (2000, OSYS)
+
+		If (CondRefOf(_OSI, Local0)) {
+			/* Linux answers _OSI with "True" for a couple of
+			 * Windows version queries. But unlike Windows it
+			 * needs a Video repost, so let's determine whether
+			 * we're running Linux.
+			 */
+
+			If (_OSI("Linux")) {
+				Store (1, LINX)
+			}
+
+			If (_OSI("Windows 2001")) {
+				Store (2001, OSYS)
+			}
+
+			If (_OSI("Windows 2001 SP1")) {
+				Store (2001, OSYS)
+			}
+
+			If (_OSI("Windows 2001 SP2")) {
+				Store (2002, OSYS)
+			}
+
+			If (_OSI("Windows 2006")) {
+				Store (2006, OSYS)
+			}
+		}
+
+		/* And the OS workarounds start right after we know what we're
+		 * running: Windows XP SP1 needs to have C-State coordination
+		 * enabled in SMM.
+		 */
+		If (LAnd(LEqual(OSYS, 2001), MPEN)) {
+			TRAP(0x3d)
+		}
+
+		/* SMM power state and C4-on-C3 settings need to be updated */
+		// TRAP(43)
+
+		/* OS Init */
+		TRAP(0x32)
+	}
+}
+
diff --git a/src/mainboard/getac/p470/acpi/superio.asl b/src/mainboard/getac/p470/acpi/superio.asl
new file mode 100644
index 0000000000..95cd1c1ed7
--- /dev/null
+++ b/src/mainboard/getac/p470/acpi/superio.asl
@@ -0,0 +1,677 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* SMSC SIO10N268 */
+
+Device (SIO1)
+{
+	Name (_HID, EISAID("PNP0A05"))
+	Name (_UID, 1)
+
+	OperationRegion(SIOR, SystemIO, 0x4e, 0x02)
+	Field (SIOR, ByteAcc, Nolock, Preserve)
+	{
+		INDX,	8,
+		DATA,	8
+	}
+
+	Mutex (SIOM, 0x00)
+
+	Method (READ, 3)
+	{
+		Acquire (SIOM, 0xffff)
+		If (LEqual(Arg0, 0)) {
+			Store (0x55, INDX)
+			Store (Arg1, INDX)
+			Store (DATA, Local1)
+			Store (0xaa, INDX)
+		}
+		And (Local1, Arg2, Local1)
+		Release(SIOM)
+		Return(Local1)
+	}
+
+	Method (WRIT, 3)
+	{
+		Acquire (SIOM, 0xffff)
+		If (LEqual(Arg0, 0)) {
+			Store (0x55, INDX)
+			Store (Arg1, INDX)
+			Store (Arg2, DATA)
+			Store (0xaa, INDX)
+		}
+		Release(SIOM)
+	}
+
+	Device (UAR1)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 1)
+		Name(_DDN, "COM1")
+		Name(_PRW, Package() { 0x08, 0x03 })
+
+		/* Device Status */
+		Method (_STA, 0)
+		{
+			Acquire (SIOM, 0xffff)
+
+			// Is the hardware enabled?
+			Store (READ(0, 0x24, 0xff), Local0)
+			If (LEqual(Local0, 0)) {
+				Return (0xd)
+			} Else {
+				// Power Enabled?
+				Store (READ(0, 0x02, 0x08), Local0)
+				If (LEqual(Local0, 0)) {
+					Return (0x0d)
+				} Else {
+					Return (0x0f)
+				}
+			}
+		}
+
+		/* Device Disable */
+		Method (_DIS, 0)
+		{
+			WRIT(0, 0x24, 0x00)
+
+			Store(READ(0, 0x28, 0x0f), Local0)
+			WRIT(0, 0x28, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x08, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+
+		/* Possible Resource Settings */
+		Name(_PRS, ResourceTemplate() {
+			StartDependentFn(0, 1) {
+				IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
+				IRQNoFlags() { 4 }
+			} EndDependentFn()
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0)
+		{
+			Name(NONE, ResourceTemplate() {
+				IO(Decode16, 0x000, 0x000, 0x0, 0x0)
+				IRQNoFlags() { }
+			})
+
+			Name(RSRC, ResourceTemplate() {
+				IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8, _IOA)
+				IRQNoFlags(_IRA) { 4 }
+			})
+
+			And (_STA(), 0x02, Local0)
+			If (LEqual(Local0, 0)) {
+				Return(NONE)
+			}
+
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.UAR1._CRS._IOA._MIN, IOLO)
+			CreateByteField(RSRC, 0x03, IOHI) // Why?
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.UAR1._CRS._IOA._MAX, IORL)
+			CreateByteField(RSRC, 0x05, IORH) // Why?
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.UAR1._CRS._IRA._INT, IRQL)
+			
+			Store (READ(0, 0x24, 0xff), Local0)
+			And (Local0, 0xc0, Local1)
+			ShiftRight(Local1, 0x06, Local1)
+			ShiftLeft(Local0, 0x02, Local0)
+			Store(Local0, IOLO)
+			Store(Local1, IOHI)
+			Store(IOLO, IORL)
+			Store(IOHI, IORH)
+
+			/* Interrupt */
+			Store(READ(0, 0x28, 0xf0), Local0)
+			ShiftRight(Local0, 4, Local0)
+			ShiftLeft(1, Local0, IRQL)
+			Return(RSRC)
+		}
+
+		/* Set Resource Settings */
+		Method(_SRS, 1)
+		{
+			CreateByteField(Arg0, 0x02, IOLO)
+			CreateByteField(Arg0, 0x03, IOHI)
+			CreateByteField(Arg0, 0x09, IRQL)
+
+			WRIT(0, 0x24, 0)
+			FindSetRightBit(IRQL, Local0)
+			Decrement(Local0)
+			ShiftLeft(Local0, 4, Local0)
+
+			Store(READ(0, 0x28, 0x0f), Local1)
+			Or(Local0, Local1, Local0)
+			WRIT(0, 0x28, Local0)
+
+			Store(IOLO, Local0)
+			ShiftRight(Local0, 2, Local0)
+			And(Local0, 0xfe, Local0)
+
+			Store(IOHI, Local1)
+			ShiftLeft(Local1, 6, Local1)
+			Or (Local0, Local1, Local0)
+			WRIT(0, 0x24, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x08, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store(READ(0, 0x07, 0xff), Local0)
+			Not(0x40, Local1)
+			And (Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+
+		/* D0 state - Line drivers are on */
+		Method (_PS0, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x08, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store (READ(0, 0x07, 0xff), Local0)
+			Not(0x40, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+		/* D3 State - Line drivers are off */
+		Method(_PS3, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x08, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+	}
+
+	Device (UAR2)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 2)
+		Name(_DDN, "COM2")
+		Name(_PRW, Package() { 0x08, 0x03 })
+
+		/* Device Status */
+		Method (_STA, 0)
+		{
+			/* IRDA? */
+			Store(READ(0, 0x0c, 0x38), Local0)
+			If (LNotEqual(Local0, Zero)) {
+				Return (0)
+			}
+
+			// Is the hardware enabled?
+			Store (READ(0, 0x25, 0xff), Local0)
+			If (LEqual(Local0, 0)) {
+				Return (0xd)
+			} Else {
+				// Power Enabled?
+				Store (READ(0, 0x02, 0x80), Local0)
+				If (LEqual(Local0, 0)) {
+					Return (0x0d)
+				} Else {
+					Return (0x0f)
+				}
+			}
+		}
+
+		/* Device Disable */
+		Method (_DIS, 0)
+		{
+			WRIT(0, 0x25, 0x00)
+
+			Store(READ(0, 0x28, 0xf0), Local0)
+			WRIT(0, 0x28, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x80, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+
+		/* Possible Resource Settings */
+		Name(_PRS, ResourceTemplate() {
+			StartDependentFn(0, 1) {
+				IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+				IRQNoFlags() { 3 }
+			} EndDependentFn()
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0)
+		{
+			Name(NONE, ResourceTemplate() {
+				IO(Decode16, 0x000, 0x000, 0x0, 0x0)
+				IRQNoFlags() { }
+			})
+
+			Name(RSRC, ResourceTemplate() {
+				IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8, _IOB)
+				IRQNoFlags(_IRB) { 3 }
+			})
+
+			And (_STA(), 0x02, Local0)
+			If (LEqual(Local0, 0)) {
+				Return(NONE)
+			}
+
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.UAR2._CRS._IOB._MIN, IOLO)
+			CreateByteField(RSRC, 0x03, IOHI)
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.UAR2._CRS._IOB._MAX, IORL)
+			CreateByteField(RSRC, 0x05, IORH)
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.UAR2._CRS._IRB._INT, IRQL)
+			
+			Store (READ(0, 0x25, 0xff), Local0)
+			And (Local0, 0xc0, Local1)
+			ShiftRight(Local1, 0x06, Local1)
+			ShiftLeft(Local0, 0x02, Local0)
+			Store(Local0, IOLO)
+			Store(Local1, IOHI)
+			Store(IOLO, IORL)
+			Store(IOHI, IORH)
+
+			/* Interrupt */
+			Store(READ(0, 0x28, 0x0f), Local0)
+			ShiftRight(Local0, 4, Local0)
+			ShiftLeft(1, Local0, IRQL)
+			Return(RSRC)
+		}
+
+		/* Set Resource Settings */
+		Method(_SRS, 1)
+		{
+			CreateByteField(Arg0, 0x02, IOLO)
+			CreateByteField(Arg0, 0x03, IOHI)
+			CreateByteField(Arg0, 0x09, IRQL)
+
+			WRIT(0, 0x25, 0)
+			FindSetRightBit(IRQL, Local0)
+			Decrement(Local0)
+
+			Store(READ(0, 0x28, 0xf0), Local1)
+			Or(Local0, Local1, Local0)
+			WRIT(0, 0x28, Local0)
+
+			Store(IOLO, Local0)
+			ShiftRight(Local0, 2, Local0)
+			And(Local0, 0xfe, Local0)
+
+			Store(IOHI, Local1)
+			ShiftLeft(Local1, 6, Local1)
+			Or (Local0, Local1, Local0)
+			WRIT(0, 0x25, Local0)
+
+			Store(READ(0, 0x0c, 0xff), Local0)
+			Not(0x38, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x0c, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x80, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store(READ(0, 0x07, 0xff), Local0)
+			Not(0x20, Local1)
+			And (Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+		/* D0 state - Line drivers are on */
+		Method (_PS0, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x80, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store (READ(0, 0x07, 0xff), Local0)
+			Not(0x20, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+		/* D3 State - Line drivers are off */
+		Method(_PS3, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x80, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+	}
+
+	Device (UAR3)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 3)
+		Name(_DDN, "COM3")
+		Name(_PRW, Package() { 0x08, 0x03 })
+
+		/* Device Status */
+		Method (_STA, 0)
+		{
+			Acquire (SIOM, 0xffff)
+
+			// Is the hardware enabled?
+			Store (READ(0, 0x1b, 0xff), Local0)
+			If (LEqual(Local0, 0)) {
+				Return (0xd)
+			} Else {
+				// Power Enabled?
+				Store (READ(0, 0x02, 0x02), Local0)
+				If (LEqual(Local0, 0)) {
+					Return (0x0d)
+				} Else {
+					Return (0x0f)
+				}
+			}
+		}
+
+		/* Device Disable */
+		Method (_DIS, 0)
+		{
+			WRIT(0, 0x1b, 0x00)
+
+			Store(READ(0, 0x1d, 0x0f), Local0)
+			WRIT(0, 0x1d, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x02, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+
+		/* Possible Resource Settings */
+		Name(_PRS, ResourceTemplate() {
+			StartDependentFn(0, 1) {
+				IO(Decode16, 0x3e8, 0x3e8, 0x8, 0x8)
+				IRQNoFlags() { 5 }
+			} EndDependentFn()
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0)
+		{
+			Name(NONE, ResourceTemplate() {
+				IO(Decode16, 0x000, 0x000, 0x0, 0x0)
+				IRQNoFlags() { }
+			})
+
+			Name(RSRC, ResourceTemplate() {
+				IO(Decode16, 0x3e8, 0x3e8, 0x8, 0x8, _IOA)
+				IRQNoFlags(_IRA) { 5 }
+			})
+
+			And (_STA(), 0x02, Local0)
+			If (LEqual(Local0, 0)) {
+				Return(NONE)
+			}
+
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.UAR3._CRS._IOA._MIN, IOLO)
+			CreateByteField(RSRC, 0x03, IOHI) // Why?
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.UAR3._CRS._IOA._MAX, IORL)
+			CreateByteField(RSRC, 0x05, IORH) // Why?
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.UAR3._CRS._IRA._INT, IRQL)
+			
+			Store (READ(0, 0x1b, 0xff), Local0)
+			And (Local0, 0xc0, Local1)
+			ShiftRight(Local1, 0x06, Local1)
+			ShiftLeft(Local0, 0x02, Local0)
+			Store(Local0, IOLO)
+			Store(Local1, IOHI)
+			Store(IOLO, IORL)
+			Store(IOHI, IORH)
+
+			/* Interrupt */
+			Store(READ(0, 0x1d, 0xf0), Local0)
+			ShiftRight(Local0, 4, Local0)
+			ShiftLeft(1, Local0, IRQL)
+			Return(RSRC)
+		}
+
+		/* Set Resource Settings */
+		Method(_SRS, 1)
+		{
+			CreateByteField(Arg0, 0x02, IOLO)
+			CreateByteField(Arg0, 0x03, IOHI)
+			CreateByteField(Arg0, 0x09, IRQL)
+
+			WRIT(0, 0x1b, 0)
+			FindSetRightBit(IRQL, Local0)
+			Decrement(Local0)
+			ShiftLeft(Local0, 4, Local0)
+
+			Store(READ(0, 0x1d, 0x0f), Local1)
+			Or(Local0, Local1, Local0)
+			WRIT(0, 0x1d, Local0)
+
+			Store(IOLO, Local0)
+			ShiftRight(Local0, 2, Local0)
+			And(Local0, 0xfe, Local0)
+
+			Store(IOHI, Local1)
+			ShiftLeft(Local1, 6, Local1)
+			Or (Local0, Local1, Local0)
+			WRIT(0, 0x1b, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x02, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store(READ(0, 0x07, 0xff), Local0)
+			Not(0x04, Local1)
+			And (Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+
+		/* D0 state - Line drivers are on */
+		Method (_PS0, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x02, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store (READ(0, 0x07, 0xff), Local0)
+			Not(0x04, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+		/* D3 State - Line drivers are off */
+		Method(_PS3, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x02, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+	}
+
+
+	Device (UAR4)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 4)
+		Name(_DDN, "COM4")
+		Name(_PRW, Package() { 0x08, 0x03 })
+
+		/* Device Status */
+		Method (_STA, 0)
+		{
+			Acquire (SIOM, 0xffff)
+
+			// Is the hardware enabled?
+			Store (READ(0, 0x1c, 0xff), Local0)
+			If (LEqual(Local0, 0)) {
+				Return (0xd)
+			} Else {
+				// Power Enabled?
+				Store (READ(0, 0x02, 0x04), Local0)
+				If (LEqual(Local0, 0)) {
+					Return (0x0d)
+				} Else {
+					Return (0x0f)
+				}
+			}
+		}
+
+		/* Device Disable */
+		Method (_DIS, 0)
+		{
+			WRIT(0, 0x1c, 0x00)
+
+			Store(READ(0, 0x1d, 0x0f), Local0)
+			WRIT(0, 0x1d, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x04, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+
+		/* Possible Resource Settings */
+		Name(_PRS, ResourceTemplate() {
+			StartDependentFn(0, 1) {
+				IO(Decode16, 0x2e8, 0x2e8, 0x8, 0x8)
+				IRQNoFlags() { 11 }
+			} EndDependentFn()
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0)
+		{
+			Name(NONE, ResourceTemplate() {
+				IO(Decode16, 0x000, 0x000, 0x0, 0x0)
+				IRQNoFlags() { }
+			})
+
+			Name(RSRC, ResourceTemplate() {
+				IO(Decode16, 0x2e8, 0x2e8, 0x8, 0x8, _IOA)
+				IRQNoFlags(_IRA) { 11 }
+			})
+
+			And (_STA(), 0x02, Local0)
+			If (LEqual(Local0, 0)) {
+				Return(NONE)
+			}
+
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.UAR4._CRS._IOA._MIN, IOLO)
+			CreateByteField(RSRC, 0x03, IOHI) // Why?
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.UAR4._CRS._IOA._MAX, IORL)
+			CreateByteField(RSRC, 0x05, IORH) // Why?
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.UAR4._CRS._IRA._INT, IRQL)
+			
+			Store (READ(0, 0x1c, 0xff), Local0)
+			And (Local0, 0xc0, Local1)
+			ShiftRight(Local1, 0x06, Local1)
+			ShiftLeft(Local0, 0x02, Local0)
+			Store(Local0, IOLO)
+			Store(Local1, IOHI)
+			Store(IOLO, IORL)
+			Store(IOHI, IORH)
+
+			/* Interrupt */
+			Store(READ(0, 0x1d, 0xf0), Local0)
+			ShiftRight(Local0, 4, Local0)
+			ShiftLeft(1, Local0, IRQL)
+			Return(RSRC)
+		}
+
+		/* Set Resource Settings */
+		Method(_SRS, 1)
+		{
+			CreateByteField(Arg0, 0x02, IOLO)
+			CreateByteField(Arg0, 0x03, IOHI)
+			CreateByteField(Arg0, 0x09, IRQL)
+
+			WRIT(0, 0x1c, 0)
+			FindSetRightBit(IRQL, Local0)
+			Decrement(Local0)
+			ShiftLeft(Local0, 4, Local0)
+
+			Store(READ(0, 0x1d, 0x0f), Local1)
+			Or(Local0, Local1, Local0)
+			WRIT(0, 0x1d, Local0)
+
+			Store(IOLO, Local0)
+			ShiftRight(Local0, 2, Local0)
+			And(Local0, 0xfe, Local0)
+
+			Store(IOHI, Local1)
+			ShiftLeft(Local1, 6, Local1)
+			Or (Local0, Local1, Local0)
+			WRIT(0, 0x1c, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x04, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store(READ(0, 0x07, 0xff), Local0)
+			Not(0x08, Local1)
+			And (Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+
+		/* D0 state - Line drivers are on */
+		Method (_PS0, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x04, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store (READ(0, 0x07, 0xff), Local0)
+			Not(0x08, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+		/* D3 State - Line drivers are off */
+		Method(_PS3, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x04, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+	}
+
+}
+
diff --git a/src/mainboard/getac/p470/acpi/thermal.asl b/src/mainboard/getac/p470/acpi/thermal.asl
new file mode 100644
index 0000000000..93bdbcfe66
--- /dev/null
+++ b/src/mainboard/getac/p470/acpi/thermal.asl
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		// TODO These could/should be read from the
+		// GNVS area, so they can be controlled by 
+		// coreboot
+		Name(TC1V, 0x00)
+		Name(TC2V, 0x0a)
+		Name(TSPV, 0x32)
+
+
+		// Convert from °C to 1/10 Kelvin
+		Method(DEGR, 1, NotSerialized)
+		{
+			Store(Arg0, Local0)
+			// 10ths of degrees
+			Multiply(Local0, 10, Local0)
+			// 0°C is 273.15 K, we need to round it.
+			Add(Local0, 2732, Local0)
+			Return(Local0)
+		}
+
+		// At which temperature should the OS start
+		// active cooling?
+		Method (_AC0, 0, Serialized)
+		{
+			Return (0xf5c) // Value for Rocky
+		}
+
+		// Critical shutdown temperature
+		Method (_CRT, 0, Serialized)
+		{
+			Store(\_SB.PCI0.LPCB.EC0.CRTT, Local0)
+			Store(DEGR(Local0), Local0)
+			Return(Local0)
+		}
+
+		// CPU throttling start temperature
+		Method (_PSV, 0, Serialized)
+		{
+			Store(\_SB.PCI0.LPCB.EC0.CTRO, Local0)
+			Store(DEGR(Local0), Local0)
+			Return(Local0)
+		}
+
+		// Get DTS Temperature
+		Method (_TMP, 0, Serialized)
+		{
+			Store(\_SB.PCI0.LPCB.EC0.CTMP, Local0)
+			Store(DEGR(Local0), Local0)
+			Return(Local0)
+		}
+
+		// Processors used for active cooling
+		Method (_PSL, 0, Serialized)
+		{
+			If (MPEN) {
+				Return (Package() {\_PR.CPU0, \_PR.CPU1})
+			}
+			Return (Package() {\_PR.CPU0})
+		}
+
+		// TC1 value for passive cooling
+		Method (_TC1, 0, Serialized)
+		{
+			Return (TC1V)
+		}
+
+		// TC2 value for passive cooling
+		Method (_TC2, 0, Serialized)
+		{
+			Return (TC2V)
+		}
+
+		// Sampling period for passive cooling
+		Method (_TSP, 0, Serialized)
+		{
+			Return (TSPV)
+		}
+	}
+}
+
diff --git a/src/mainboard/getac/p470/acpi/video.asl b/src/mainboard/getac/p470/acpi/video.asl
new file mode 100644
index 0000000000..507a390d27
--- /dev/null
+++ b/src/mainboard/getac/p470/acpi/video.asl
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+	// TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+	// TODO (no displays defined yet)
+}
+