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authorArthur Heymans <arthur@aheymans.xyz>2019-01-10 23:13:11 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-06-06 10:38:22 +0000
commit5eb81bed2ea503aaf910430da492ed75d27ef94f (patch)
tree562c5611149b81c7b81d96c242feff2fe3dede78 /src/mainboard/foxconn
parentfefe7afeb0abb9d779f1e3b025dde6e1164dac9d (diff)
sb/intel/i82801gx: Detect if the southbridge supports AHCI
This automatically detects whether the southbridge supports AHCI. If AHCI support is selected it will be used unless "sata_no_ahci" is set in the devicetree to override the behavior. Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/foxconn')
-rw-r--r--src/mainboard/foxconn/d41s/devicetree.cb1
-rw-r--r--src/mainboard/foxconn/g41s-k/devicetree.cb1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb
index 75df88e5c6..a611ee35c5 100644
--- a/src/mainboard/foxconn/d41s/devicetree.cb
+++ b/src/mainboard/foxconn/d41s/devicetree.cb
@@ -40,7 +40,6 @@ chip northbridge/intel/pineview # Northbridge
register "pirqf_routing" = "0x0b"
register "pirqg_routing" = "0x0b"
register "pirqh_routing" = "0x0b"
- register "sata_ahci" = "0x1"
register "sata_ports_implemented" = "0x3"
register "gpe0_en" = "0x441"
diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb
index ca952ba7c6..b196e24961 100644
--- a/src/mainboard/foxconn/g41s-k/devicetree.cb
+++ b/src/mainboard/foxconn/g41s-k/devicetree.cb
@@ -47,7 +47,6 @@ chip northbridge/intel/x4x # Northbridge
register "ide_enable_primary" = "0x0"
register "ide_enable_secondary" = "0x0"
- register "sata_ahci" = "0x0" # AHCI does not work
register "sata_ports_implemented" = "0x3"
device pci 1b.0 on end # Audio