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authorArthur Heymans <arthur@aheymans.xyz>2018-04-10 15:18:38 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-01-23 14:49:57 +0000
commit84fdda381224f0371e27ef3f0ad77ee1103cb05a (patch)
tree08aa40dd49e214fe0fd05b7960ba3b3c00e55ccb /src/mainboard/foxconn
parentc82950bf79285fa838b6fbaf019a5638316ba053 (diff)
nb/intel/pineview: Use parallel MP init
Remove guards around CPU code on which all platforms use parallel MP init code. This removes the option to disable HT siblings. Tested on Foxconn D41S. Change-Id: I89f7d514d75fe933c3a8858da37004419189674b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25602 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/foxconn')
-rw-r--r--src/mainboard/foxconn/d41s/cmos.layout1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/foxconn/d41s/cmos.layout b/src/mainboard/foxconn/d41s/cmos.layout
index 9b9a084fc0..b006973cc3 100644
--- a/src/mainboard/foxconn/d41s/cmos.layout
+++ b/src/mainboard/foxconn/d41s/cmos.layout
@@ -44,7 +44,6 @@ entries
416 512 s 0 boot_devices
# coreboot config options: cpu
-944 1 e 2 hyper_threading
#945 7 r 0 unused
# coreboot config options: northbridge