diff options
author | Duncan Laurie <dlaurie@google.com> | 2018-09-26 21:11:58 +0000 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-04 09:36:59 +0000 |
commit | ecf6531c47f77cae0e5d1349319b1f2c997e994f (patch) | |
tree | 9da5766e8ca9fb3e9f5c3fae329dfa46de53daf7 /src/mainboard/foxconn/g41s-k | |
parent | d5de063dffe5c0daa56453f669af65dde09e446a (diff) |
ec/google/chromeec: Define a sync IRQ if needed
Some boards are adding a second pin used for synchronization between
the EC and AP. This is a direct connection between the EC and the SOC
that is intended to provide a lower latency interrupt signal for
sensors on the EC.
Currently the runtime EC interrupts assert an SCI before eventually
resulting in a Notify() on the MKBP device that the sensor driver users.
These extra layers add processing time and require additional EC
communication to determine the event source.
This interface was tested on a reworked Nocturne board with modified
EC and a modified kernel driver to ensure that the interrupt asserts
as expected and can be used by the kernel driver.
Change-Id: I49a11363ce82882e572bcb8923fd114ab6593fea
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/28758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/foxconn/g41s-k')
0 files changed, 0 insertions, 0 deletions