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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2021-04-14 14:01:02 +0530
committerPatrick Georgi <pgeorgi@google.com>2021-04-16 06:44:28 +0000
commit6935350ad6610fca943afc4ae96125760538f98c (patch)
tree74fddae9ea7c1f6d79c09821a04aa6ec8486264d /src/mainboard/foxconn/g41s-k/Kconfig
parentba0ab9f1f52f64906beaa6ebf079864b07f6f43e (diff)
soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OC
We need to change OC pin for type C USB3 ports and it depends on the board design. Allowing it to be filled by devicetree will make it easier to change the mapping based on the board design BUG=b:184653645 BRANCH=None TEST=compilation works fine and value of UPD is getting reflected. Change-Id: I61faa661c12dced27c6cdd7005a61ae8de8621e1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/foxconn/g41s-k/Kconfig')
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