diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 13:52:11 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2023-01-30 10:49:11 +0000 |
| commit | 69cd729c0cde6f15d1de692f5a2da5d3dfe8ba15 (patch) | |
| tree | 4f21a3de147f422336545ed3164581b6b80c45d7 /src/mainboard/facebook | |
| parent | 0a97e466163dda4e55c1eda145646054dcd8dd06 (diff) | |
mb/*: Remove lapic from devicetree
The parallel mp code picks up lapics at runtime, so remove it from all
devicetrees that use this codebase.
Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/facebook')
| -rw-r--r-- | src/mainboard/facebook/fbg1701/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/facebook/monolith/devicetree.cb | 4 |
2 files changed, 2 insertions, 6 deletions
diff --git a/src/mainboard/facebook/fbg1701/devicetree.cb b/src/mainboard/facebook/fbg1701/devicetree.cb index a340fdc37c..a77a6405f7 100644 --- a/src/mainboard/facebook/fbg1701/devicetree.cb +++ b/src/mainboard/facebook/fbg1701/devicetree.cb @@ -82,9 +82,7 @@ chip soc/intel/braswell # CPLD requires continuous mode register "serirq_mode" = "SERIRQ_CONTINUOUS" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # 8086 2280 - SoC router diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 05bcc12257..a4a090674e 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -212,9 +212,7 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device |