mb/facebook/monolith: Add Facebook Monolith

The board is booting Linux and has been briefly tested.

SeaBIOS, TianoCore payload and Linux as payload all seem to work fine.

BUG=N/A
TEST=tested on Facebook Monolith

Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>

4 files changed, 140 insertions, 0 deletions

diff --git a/src/mainboard/facebook/monolith/acpi/dptf.asl b/src/mainboard/facebook/monolith/acpi/dptf.asl
new file mode 100644
index 0000000000..5ea95b41d0
--- /dev/null
+++ b/src/mainboard/facebook/monolith/acpi/dptf.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE        80
+#define DPTF_CPU_CRITICAL       90
+#define DPTF_CPU_ACTIVE_AC0     90
+#define DPTF_CPU_ACTIVE_AC1     80
+#define DPTF_CPU_ACTIVE_AC2     70
+#define DPTF_CPU_ACTIVE_AC3     60
+#define DPTF_CPU_ACTIVE_AC4     50
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		1600,	/* PowerLimitMinimum */
+		15000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		8000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
+
+/* Include DPTF */
+#include <soc/intel/skylake/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/facebook/monolith/acpi/ec.asl b/src/mainboard/facebook/monolith/acpi/ec.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/facebook/monolith/acpi/ec.asl
diff --git a/src/mainboard/facebook/monolith/acpi/mainboard.asl b/src/mainboard/facebook/monolith/acpi/mainboard.asl
new file mode 100644
index 0000000000..2a3ad59b9f
--- /dev/null
+++ b/src/mainboard/facebook/monolith/acpi/mainboard.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ * Copyright (C) 2018-2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB)
+{
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C"))
+		Name (_UID, 1)
+	}
+}
+
+/*
+ * Onboard CPLD
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+	Device (CPLD)		/* Onboard CPLD */
+	{
+		Name(_HID, EISAID("PNP0C01"))
+		Name(_CRS, ResourceTemplate()
+		{
+			/* Reserve 0x280 to 0x2BF for the CPLD */
+			FixedIO (0x0280, 0x40)
+			IRQNoFlags () {7}
+		})
+	}
+}
diff --git a/src/mainboard/facebook/monolith/acpi/superio.asl b/src/mainboard/facebook/monolith/acpi/superio.asl
new file mode 100644
index 0000000000..0f5790da8d
--- /dev/null
+++ b/src/mainboard/facebook/monolith/acpi/superio.asl
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018-2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+
+Device (COM1) {
+	Name (_HID, EISAID ("PNP0501"))
+	Name (_UID, 1)
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+
+	Name (_CRS, ResourceTemplate ()
+	{
+		FixedIO (0x03F8, 0x08)
+		FixedIO (0x6E, 0x02)
+		IRQNoFlags () {4}
+	})
+
+	Name (_PRS, ResourceTemplate ()
+	{
+		StartDependentFn (0, 0) {
+			FixedIO (0x03F8, 0x08)
+			FixedIO (0x6E, 0x02)
+			IRQNoFlags () {4}
+		}
+		EndDependentFn ()
+	})
+}