diff options
| author | Frans Hendriks <fhendriks@eltan.com> | 2019-06-04 13:53:05 +0200 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2019-06-05 13:03:43 +0000 |
| commit | 43b6e2ed7108859297512a6d4194335fb8237d1b (patch) | |
| tree | 26163bc7aa32cb13bffabee2092f2f1550118dac /src/mainboard/facebook/fbg1701/onboard.h | |
| parent | d622507450464db5ee6cff7de03f9649a299018b (diff) | |
mainboard/facebook/fbg1701: Do initial mainboard commit
Initial support for Facebook FBG-1701 system.
coreboot implementation based on Intel Strago mainboard.
Configure 'Onboard memory manufacturer' which must match HW.
BUG=N/A
TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701
Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/facebook/fbg1701/onboard.h')
| -rw-r--r-- | src/mainboard/facebook/fbg1701/onboard.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h new file mode 100644 index 0000000000..d1fd0509a6 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/onboard.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +/* SD CARD gpio */ +#define SDCARD_CD 81 /* Not used */ + +#define ITE8528_CMD_PORT 0x6E +#define ITE8528_DATA_PORT 0x6F + +/* CPLD definitions */ +#define CPLD_PCB_VERSION_PORT 0x283 +#define CPLD_PCB_VERSION_MASK 0xF0 +#define CPLD_PCB_VERSION_BIT 4 + +#define CPLD_RESET_PORT 0x287 +#define CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE 0x20 +#define CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE 0x00 + +#endif |