arch/riscv: Add include/arch/barrier.h

mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/.
It is currently provided by atomic.h, but I think it fits better into
barrier.h.

The "fence" instruction represents a full memory fence, as opposed to
variants such as "fence r, rw" which represent a partial fence. An
operating system might want to use precisely the right fence, but
coreboot doesn't need this level of performance at the cost of
simplicity.

Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15830
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

2 files changed, 4 insertions, 2 deletions

diff --git a/src/mainboard/emulation/qemu-riscv/qemu_util.c b/src/mainboard/emulation/qemu-riscv/qemu_util.c
index fca7d56ed0..3c2941ce72 100644
--- a/src/mainboard/emulation/qemu-riscv/qemu_util.c
+++ b/src/mainboard/emulation/qemu-riscv/qemu_util.c
@@ -25,11 +25,12 @@
  * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
  */
 
-#include <spike_util.h>
+#include <arch/barrier.h>
 #include <arch/errno.h>
 #include <atomic.h>
-#include <string.h>
 #include <console/console.h>
+#include <spike_util.h>
+#include <string.h>
 
 uintptr_t translate_address(uintptr_t vAddr) {
 	// TODO: implement the page table translation algorithm
diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c
index 358cb4428e..f0f5301814 100644
--- a/src/mainboard/emulation/spike-riscv/spike_util.c
+++ b/src/mainboard/emulation/spike-riscv/spike_util.c
@@ -26,6 +26,7 @@
  */
 
 #include <spike_util.h>
+#include <arch/barrier.h>
 #include <arch/errno.h>
 #include <atomic.h>
 #include <string.h>