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authorAamir Bohra <aamir.bohra@intel.com>2020-03-23 10:13:10 +0530
committerFurquan Shaikh <furquan@google.com>2020-04-01 19:12:30 +0000
commit555c9b6268febf001e887fbb9e3c3f0901a371ac (patch)
treed3b1968356086c05ac0894115f45b06cb8437e85 /src/mainboard/emulation
parenta23e0c9d74b7f06738ebf28b068e1bd63f246982 (diff)
soc/intel/tigerlake: Remove Jasper Lake SoC references
This implementation removes all JSL references from the TGL SoC code. Additionally, mainboard code changes are done to support build. BUG=b:150217037 TEST=build tglrvp and volteer Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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