diff options
| author | Frans Hendriks <fhendriks@eltan.com> | 2021-01-26 12:08:18 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-28 09:30:32 +0000 |
| commit | 2659d4090546bab463853ae6c5874f562b81fbde (patch) | |
| tree | 7097a5e98b95de979b9c48547c6700a725221a1b /src/mainboard/emulation | |
| parent | ca083db4d377cdfeca61ad97b33efadc0f9ccf36 (diff) | |
mb/emulation/qemu-q35: Solve lint-001 error
lint-001-no-global-config-in-romstage error on
D0F0_PCIEXBAR_LO.
DOF0_PCIEXBAR_LO is defined in bootblock.c and
romstage.c.
Place D0F0_PCIEXBAR_XX in local gm35.h.
BUG = N/A
TEST = Build and boot QEMU x86 q35/ich9
Change-Id: Ia5ac9eb797de996186282193647313b9f7b42624
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Diffstat (limited to 'src/mainboard/emulation')
| -rw-r--r-- | src/mainboard/emulation/qemu-q35/bootblock.c | 4 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-q35/gm35.h | 9 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-q35/romstage.c | 2 |
3 files changed, 11 insertions, 4 deletions
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index efb3a4f7e1..6de3dd820b 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -6,9 +6,7 @@ #include <southbridge/intel/i82801ix/i82801ix.h> #include <console/console.h> -/* Just define these here, there is no gm35.h file to include. */ -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 +#include "gm35.h" static void bootblock_northbridge_init(void) { diff --git a/src/mainboard/emulation/qemu-q35/gm35.h b/src/mainboard/emulation/qemu-q35/gm35.h new file mode 100644 index 0000000000..62b04b8625 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/gm35.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_EMU_GM35_H__ +#define __MAINBOARD_EMU_GM35_H__ + +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 + +#endif diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 504c655c5c..92b6113427 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -6,7 +6,7 @@ #include <southbridge/intel/i82801ix/i82801ix.h> #include <device/pci_ops.h> -#define D0F0_PCIEXBAR_LO 0x60 +#include "gm35.h" static void mainboard_machine_check(void) { |