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authorRocky Phagura <rphagura@fb.com>2020-05-23 20:29:00 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-06-02 07:37:08 +0000
commitc62c98a884231ef36bf3eb613b2d24e37c89c4d2 (patch)
tree031e3f0a1cd9f4d5c7b578b08174a9001ef18710 /src/mainboard/emulation
parenta895344936594402175b2f4321b0e1a9d5dbfe7b (diff)
soc/intel/xeon_sp: Early programming of ACPI bar
ACPI bar was not programmed previously for which is needed to enable SMI's and to check SMI status registers. The architecture of Lewisburg PCH is very similar to SunrisePoint PCH thus we can use code from soc/intel/skylake. TEST=build for Tiogapass and check ACPI base. Log message will now show pmbase=501 (bit 0 is enable) instead of 0. Check by reading and writing to io port 0x500. Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379 Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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