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| author | Taniya Das <tdas@codeaurora.org> | 2019-11-05 21:37:32 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-16 09:39:17 +0000 |
| commit | ece88ab765859b728c2ba17d1224455807a5fda6 (patch) | |
| tree | 218ba19702d6731f340ef9de7610c08376578dfd /src/mainboard/emulation/spike-riscv | |
| parent | 98579a9e86b341bc6827bdbb56583584981b8204 (diff) | |
sc7180: clock: Add support for QUP DFSR configuration
Support configuring the qup dfsr registers.
Tested: validated DFSR clock configuration and M/N/D values.
Change-Id: I146ac7c2197606965265f2a770769312af76041e
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv')
0 files changed, 0 insertions, 0 deletions