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| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2020-06-04 19:39:30 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-05 19:51:47 +0000 |
| commit | 017ec1658833c38a0cdcf5e170bc3a9dfb5f38bd (patch) | |
| tree | 69ee11360850c0d28e9fc5e0ef6bfd20778e400c /src/mainboard/emulation/spike-riscv | |
| parent | 466374924ccfc3c1306ca030b62d1de5ba3a1fba (diff) | |
soc/amd/common/spi: add and use define for last FIFO position
The existing define for SPI_FIFO_DEPTH looked a bit suspicious, but
turned out to be correct.
Change-Id: I91e65d922673f5c451a336ae013cb75f87a3fc98
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv')
0 files changed, 0 insertions, 0 deletions