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authorNico Huber <nico.huber@secunet.com>2017-07-19 15:45:14 +0200
committerNico Huber <nico.h@gmx.de>2017-07-20 15:44:59 +0000
commit9dc62ea133d826cf88ccd29e579ea976257d5487 (patch)
treef162714260ea26cbf2637cde5bd4e39fecc800d5 /src/mainboard/emulation/spike-riscv
parentfb66e81e6c58b0825e85b2c0afabbe032f103d6e (diff)
soc/intel/skylake: Fix broken memory info HOB scanning
It looks like this code was written with completely different semantics in mind. Controllers, channels and DIMMs are all presented in their phy- sical order (i.e. gaps are not closed). So we have to look at the whole structure and not only the first n respective entries. Change-Id: I8a9039f73f1befdd09c1fc8e17cd3f6e08e0cd47 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20650 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv')
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