diff options
| author | John Zhao <john.zhao@intel.com> | 2020-07-17 11:36:00 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-26 21:43:36 +0000 |
| commit | 7417bb0e5a8bddbf9a56b990119fa3af56e663ac (patch) | |
| tree | 476bd12831a6794a98f8e5727aae0eedca8928c6 /src/mainboard/emulation/spike-riscv | |
| parent | ec321094f68d3fbfd13b2514aaa6405b1bcd4886 (diff) | |
soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platform
Enabling VT-d on pre-QS silicon may have issues like rendering the
Thunderbolt driver useless. This change will ensure that VT-d is
disabled for pre-QS silicon and enabled for QS.
BUG=b:152242800,161215918,158519322
TEST=Validated VT-d is disabled for pre-QS (cpu:0x806c0) and enabled for
QS (cpu:0x806c1). Kernel walks through ACPI tables. If VT-d is disabled
and no DMAR table exists, IOMMU will not be enabled.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I98a9f6df185002a4e68eaa910f867acd0b96ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv')
0 files changed, 0 insertions, 0 deletions