diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-03-24 16:53:37 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-03-29 18:57:28 +0000 |
| commit | 95b3dc3da9b10cb3445fdd789bfdfb0615f16ef4 (patch) | |
| tree | 749f7b336deab304b42540a4bde8c74a2967ac29 /src/mainboard/emulation/spike-riscv | |
| parent | f4e90e8a611a8ce29e3a990923ccdb99b919c21c (diff) | |
soc/amd/cezanne: Implement PROVIDES_ROM_SHARING
BUG=none
TEST=Build guybrush and verified with the PPR that the register and bits
are still the same
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0619f84cf82cbb90ded9dfd58afa6acc9520fb8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv')
0 files changed, 0 insertions, 0 deletions