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| author | Aaron Durbin <adurbin@chromium.org> | 2016-11-04 10:07:14 -0500 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-11-06 18:14:29 +0100 |
| commit | 7d9068fe0b5d87fe3fe075d5d9a5f7493f5b1eac (patch) | |
| tree | ae9b6a540a055222398a830e9b84dda9b832d652 /src/mainboard/emulation/spike-riscv | |
| parent | d5be4e3d7e7d092d3ea9dc98738c39ea43d3f738 (diff) | |
soc/intel/common: log event when MRC cache is updated
Log when the MRC cache is attempted to be updated with status
of success or failure. Just one slot is supported currently
which is deemed 'normal'. This is because there are more slots
anticipated in the future.
BUG=chrome-os-partner:59395
Change-Id: I0f81458325697aff9924cc359a4173e0d35da5da
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17231
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/emulation/spike-riscv')
0 files changed, 0 insertions, 0 deletions