diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-04 20:32:15 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-11 11:42:26 +0000 |
| commit | 8245bd25a35466248c00bc7a4d0cf96f8391924a (patch) | |
| tree | 5e3cc97038c161661fdaa0015ad37f1d73f4219c /src/mainboard/emulation/spike-riscv | |
| parent | ad27283a3c777f288254974cac233e47d1c0005d (diff) | |
fmap: Make FMAP_CACHE mandatory if it is configured in
Now that we have a CONFIG_NO_FMAP_CACHE to completely configure out the
pre-RAM FMAP cache code, there's no point in allowing the region to be
optional anymore. This patch makes the section required by the linker.
If a board doesn't want to provide it, it has to select NO_FMAP_CACHE.
Adding FMAP_CACHE regions to a couple more targets that I think can use
them but I don't know anything about... please yell if one of these is
a bad idea and I should mark them NO_FMAP_CACHE instead.
Change-Id: Ic7d47772ab3abfa7e3a66815c3739d0af071abc2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv')
| -rw-r--r-- | src/mainboard/emulation/spike-riscv/memlayout.ld | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index bae414ffd5..b6e4d9d5e8 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -24,7 +24,8 @@ SECTIONS DRAM_START(START) BOOTBLOCK(START, 64K) STACK(START + 8M, 4K) - /* hole at (START + 8M + 4K, 60K) */ + FMAP_CACHE(START + 8M + 4K, 2K) + /* hole at (START + 8M + 6K, 58K) */ ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) RAMSTAGE(START + 8M + 200K, 256K) |