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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2016-08-22 19:37:15 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2016-08-23 23:43:56 +0200 |
| commit | 3965a522c23ea50b1a861b89a8215a524caa35f7 (patch) | |
| tree | c69e71c15b08c8b9ddfe60f9d11d203467dad747 /src/mainboard/emulation/spike-riscv | |
| parent | b6648cd888f1ba8e0e81c59f296028ba831c6eae (diff) | |
arch/riscv: Enable U-mode/S-mode counters (stime, etc.)
Change-Id: Ie62f60b2e237fa4921384e3894569ae29639f563
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16262
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv')
0 files changed, 0 insertions, 0 deletions