diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2020-07-16 00:41:50 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-07-23 15:30:51 +0000 |
| commit | d90616278c16f3b4316eea14259917e77f8de5ca (patch) | |
| tree | a032e944b60496a7ab0fd28e5af3f5a7813df5f4 /src/mainboard/emulation/spike-riscv | |
| parent | dcee4b6fa95d52d78f068ee3bac4147b8c9f074a (diff) | |
mb/google/dedede/var/drawcia: Generate SPD ID for supported parts
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
H9HCNNNBKMMLXR-NEE
K4U6E3S4AA-MGCR
BUG=None
TEST=Build the drawcia board.
Change-Id: Id05c0b2a87b64bfedc761949cbc8ad6cf7dd73a5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43505
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv')
0 files changed, 0 insertions, 0 deletions