diff options
| author | Jan Samek <jan.samek@siemens.com> | 2023-01-26 10:14:55 +0100 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2023-01-30 16:23:54 +0000 |
| commit | f58abca47a48c3f3e6cee2599b1fcb7619865169 (patch) | |
| tree | 8fa17c3091d29aa01ba7c0a1ad6b9611d2a95466 /src/mainboard/emulation/spike-riscv/uart.c | |
| parent | 6ac0a46bbf9e20c8412ee0d04658b3a2b10d0734 (diff) | |
mb/siemens/mc_ehl3/gpio.c: Disable PSE GBE0 GPIO
Since the PSE GBE0 MAC has been disabled on this board in
commit 343644006f89 ("mb/siemens/mc_ehl3/devicetree.cb:
Remove TSN GbE 0"), therefore disable the corresponding
GPIOs as well.
BUG=none
TEST=Test link detection and IP assignment on the remaining
ports (PSE GBE1 and PCH GBE0) of mc_ehl3.
Change-Id: Ifa055f58894688471d68b9b93fcb994fdcb2a568
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72449
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv/uart.c')
0 files changed, 0 insertions, 0 deletions