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author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2016-06-10 19:35:15 +0200 |
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committer | Martin Roth <martinroth@google.com> | 2016-06-12 12:42:32 +0200 |
commit | 1282b8d99692ddfff5b78b03938b9b3555b17c00 (patch) | |
tree | c8141a7cd0789c9b24c4da9a7065312fe13fefa1 /src/mainboard/emulation/spike-riscv/uart.c | |
parent | f934efc9f8e2fe0791f47e7088301199629827b1 (diff) |
arch/riscv: Compile with -mcmodel=medany
In the default (medlow) code model, pointers are loaded with a lui, addi
instruction sequence:
lui a0, 0xNNNNN
addi a0, a0, 0xNNN
Since lui sign-extends bits 32-63 from bit 31 on RV64, lui/addi can't
load pointers just above 0x80000000, where RISC-V's RAM now lives.
The medany code model gets around this restriction by loading pointers
trough auipc and addi:
auipc a0, 0xNNNNN
addi a0, a0, 0xNNN
This way, any pointer within the current pc ±2G can be loaded, which is
by far sufficient for coreboot.
Change-Id: I77350d9218a687284c1337d987765553cf915a22
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15148
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv/uart.c')
0 files changed, 0 insertions, 0 deletions