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author | Aamir Bohra <aamir.bohra@intel.com> | 2019-07-12 14:37:55 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2019-07-16 05:40:23 +0000 |
commit | f5202a640b8f032936c831627a83a356108d94e6 (patch) | |
tree | 157304729525cd24d3d3b053a5df89600e271778 /src/mainboard/emulation/spike-riscv/mainboard.c | |
parent | cc8e992fc3a6bf2e109ad9810296a67115a327aa (diff) |
soc/intel/common/block/i2c: Set controller state to active in i2c init
Set the controller state to D0 during the i2c init sequence, this ensures
the controller is up and active.
BUG=b:135941367
TEST=Verify no timeouts seen during I2C controller enumeration sequence
Change-Id: I247ede44b8d1d6871e3e813b63f99a7f6398dd72
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34273
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv/mainboard.c')
0 files changed, 0 insertions, 0 deletions