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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2020-11-30 13:52:42 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2020-12-01 16:01:44 +0000 |
| commit | 2b77112e66d9d1678e68b7513bc916d49230993f (patch) | |
| tree | 21e0125f0f6572666cb462a6a1c57160d3df1295 /src/mainboard/emulation/spike-riscv/clint.c | |
| parent | 0e3884cfffec6e8edc9d29ee21820d896a9fa2be (diff) | |
soc/intel/common/block/cpu/car/cache_as_ram: Add x86_64 support
Doesn't affect x86_32.
Tested on Intel Skylake. Boots into bootblock and console is working.
Change-Id: I1b36ca8816dab9d30754aadd230c136978e3b344
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48170
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv/clint.c')
0 files changed, 0 insertions, 0 deletions