diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2013-01-07 13:21:22 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-01-08 23:33:35 +0100 |
| commit | 597ff87574b11dc1163eb152e0941a2cbce5341b (patch) | |
| tree | 3205d41368b0bd2a1936c795d668b43761292872 /src/mainboard/emulation/qemu-x86/northbridge.c | |
| parent | c01990789f533316e10c5fc3b5ca08ae866b8033 (diff) | |
qemu-x86: Implement more features
This patch switches the Qemu target to use (pseudo) Cache As RAM
and enables some ACPI code. This allows to use the CBMEM console
and timestamp code with coreboot in Qemu. Right now, the ACPI code
is commented out because leaving it in breaks IDE.
Change-Id: Ie20f3ecc194004f354ae3437b9cf9175382cadf8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2113
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/emulation/qemu-x86/northbridge.c')
| -rw-r--r-- | src/mainboard/emulation/qemu-x86/northbridge.c | 16 |
1 files changed, 1 insertions, 15 deletions
diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c index 16dcc3b205..6d73585cf5 100644 --- a/src/mainboard/emulation/qemu-x86/northbridge.c +++ b/src/mainboard/emulation/qemu-x86/northbridge.c @@ -14,21 +14,7 @@ #include <cbmem.h> #endif -#define CMOS_ADDR_PORT 0x70 -#define CMOS_DATA_PORT 0x71 -#define HIGH_RAM_ADDR 0x35 -#define LOW_RAM_ADDR 0x34 - -static unsigned long qemu_get_memory_size(void) -{ - unsigned long tomk; - outb (HIGH_RAM_ADDR, CMOS_ADDR_PORT); - tomk = ((unsigned long) inb(CMOS_DATA_PORT)) << 14; - outb (LOW_RAM_ADDR, CMOS_ADDR_PORT); - tomk |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6; - tomk += 16 * 1024; - return tomk; -} +#include "memory.c" static void cpu_pci_domain_set_resources(device_t dev) { |