diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2013-01-07 13:21:22 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-01-08 23:33:35 +0100 |
| commit | 597ff87574b11dc1163eb152e0941a2cbce5341b (patch) | |
| tree | 3205d41368b0bd2a1936c795d668b43761292872 /src/mainboard/emulation/qemu-x86/devicetree.cb | |
| parent | c01990789f533316e10c5fc3b5ca08ae866b8033 (diff) | |
qemu-x86: Implement more features
This patch switches the Qemu target to use (pseudo) Cache As RAM
and enables some ACPI code. This allows to use the CBMEM console
and timestamp code with coreboot in Qemu. Right now, the ACPI code
is commented out because leaving it in breaks IDE.
Change-Id: Ie20f3ecc194004f354ae3437b9cf9175382cadf8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2113
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/emulation/qemu-x86/devicetree.cb')
| -rw-r--r-- | src/mainboard/emulation/qemu-x86/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/emulation/qemu-x86/devicetree.cb b/src/mainboard/emulation/qemu-x86/devicetree.cb index 4c64d4a1d9..50f4b11917 100644 --- a/src/mainboard/emulation/qemu-x86/devicetree.cb +++ b/src/mainboard/emulation/qemu-x86/devicetree.cb @@ -7,7 +7,7 @@ chip mainboard/emulation/qemu-x86 device pci 01.1 on end register "ide0_enable" = "1" register "ide1_enable" = "1" + register "gpo" = "0x7fffbbff" end - end end |