diff options
| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-10-04 18:55:40 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-10-04 18:55:40 +0000 |
| commit | 24796fd364176ce8bb4f4eb727e0ba2ece188c08 (patch) | |
| tree | 08b54626dd61f7c0dddab795ff0025acd71eefe8 /src/mainboard/emulation/qemu-x86/Config.lb | |
| parent | 70b0cf23ce18371be96062476e4fdc88d4930683 (diff) | |
This does away with CONFIG_ROM_PAYLOAD_START and CONFIG_PAYLOAD_SIZE.
Both were only really used in pre-cbfs, as the payload's size isn't
relevant for the build process anymore.
Various calculations in {no,}failovercalculation.lb are adapted
accordingly.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/emulation/qemu-x86/Config.lb')
| -rw-r--r-- | src/mainboard/emulation/qemu-x86/Config.lb | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/src/mainboard/emulation/qemu-x86/Config.lb b/src/mainboard/emulation/qemu-x86/Config.lb index 78e5936ffc..52d2e3e7de 100644 --- a/src/mainboard/emulation/qemu-x86/Config.lb +++ b/src/mainboard/emulation/qemu-x86/Config.lb @@ -6,19 +6,12 @@ default CONFIG_USE_DCACHE_RAM=0 ## default CONFIG_ROM_SIZE = 256 * 1024 default CONFIG_ROM_SECTION_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_ROM_SECTION_OFFSET = 0 - -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_PAYLOAD_SIZE = ( CONFIG_ROM_SIZE - CONFIG_ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) +default CONFIG_ROM_SECTION_OFFSET = CONFIG_ROM_SIZE - CONFIG_ROM_SECTION_SIZE ## ## Compute where this copy of coreboot will start in the boot rom ## -default CONFIG_ROMBASE = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE ) +default CONFIG_ROMBASE = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) ## ## Compute a range of ROM that can cached to speed up coreboot, |