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author | David Milosevic <David.Milosevic@9elements.com> | 2023-11-16 05:11:18 +0100 |
---|---|---|
committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-06-08 20:41:14 +0000 |
commit | ad83eb1ee6bb833783c4b870c86413978fb5d4ba (patch) | |
tree | 34effa2a8c4d42be4b5b06dba8ad0a7b78ef8778 /src/mainboard/emulation/qemu-sbsa/memlayout.ld | |
parent | 91cda2af74b4142bf459f7416b8f997c7d981e13 (diff) |
mainboard/emulation/qemu-sbsa: Add qemu-sbsa board
Add coreboot support for qemu's sbsa-ref (Server Base System
Architecture) machine (-m sbsa-ref).
The qemu-sbsa coreboot port runs on EL2 and is the payload of the
EL3 firmware (Arm Trusted Firmware).
Note that, coreboot expects a pointer to the FDT in x0. Make sure
to configure TF-A to handoff the FDT pointer.
Example qemu commandline:
qemu-system-aarch64 -nographic -m 2048 -M sbsa-ref \
-pflash <path/to/TFA.fd> \
-pflash <path/to/coreboot.rom>
The Documentation can be found here:
Documentation/mainboard/emulation/qemu-sbsa.md
Change-Id: Iacc9aaf065e0d153336cbef9a9b5b46a9eb24a53
Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/mainboard/emulation/qemu-sbsa/memlayout.ld')
-rw-r--r-- | src/mainboard/emulation/qemu-sbsa/memlayout.ld | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/mainboard/emulation/qemu-sbsa/memlayout.ld b/src/mainboard/emulation/qemu-sbsa/memlayout.ld new file mode 100644 index 0000000000..d178521b6e --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/memlayout.ld @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* + * Memory map for QEMU sbsa-ref machine since + * [hw/arm/sbsa-ref.c, c6f3cbca32bde9ee94d9949aa63e8a7ef2d7bc5b] + */ +SECTIONS +{ + REGION(flash, 0x10000000, CONFIG_ROM_SIZE, 8) + + DRAM_START(0x10000000000) + BOOTBLOCK(0x10020010000, 64K) + STACK(0x10020020000, 54K) + CBFS_MCACHE(0x1002002D800, 8K) + FMAP_CACHE(0x1002002F800, 2K) + TIMESTAMP(0x10020030000, 1K) + TTB(0x10020070000, 128K) + RAMSTAGE(0x100200b0000, 16M) + REGION(fdt_pointer, 0x100210b0000, ARCH_POINTER_ALIGN_SIZE, ARCH_POINTER_ALIGN_SIZE) + + POSTRAM_CBFS_CACHE(0x10021200000, 1M) +} |