diff options
| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2016-07-26 01:54:34 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-02 23:35:49 +0200 |
| commit | cc5be8b72ba5b072030fdd1d382d7156da43114f (patch) | |
| tree | cb94bc583e87b6c58bdf675fdec363003d316227 /src/mainboard/emulation/qemu-riscv | |
| parent | aded214e74bcb63990d69551bec7ab03c6785b08 (diff) | |
arch/riscv: Add include/arch/barrier.h
mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/.
It is currently provided by atomic.h, but I think it fits better into
barrier.h.
The "fence" instruction represents a full memory fence, as opposed to
variants such as "fence r, rw" which represent a partial fence. An
operating system might want to use precisely the right fence, but
coreboot doesn't need this level of performance at the cost of
simplicity.
Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15830
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/emulation/qemu-riscv')
| -rw-r--r-- | src/mainboard/emulation/qemu-riscv/qemu_util.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/emulation/qemu-riscv/qemu_util.c b/src/mainboard/emulation/qemu-riscv/qemu_util.c index fca7d56ed0..3c2941ce72 100644 --- a/src/mainboard/emulation/qemu-riscv/qemu_util.c +++ b/src/mainboard/emulation/qemu-riscv/qemu_util.c @@ -25,11 +25,12 @@ * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. */ -#include <spike_util.h> +#include <arch/barrier.h> #include <arch/errno.h> #include <atomic.h> -#include <string.h> #include <console/console.h> +#include <spike_util.h> +#include <string.h> uintptr_t translate_address(uintptr_t vAddr) { // TODO: implement the page table translation algorithm |