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| author | Patrick Georgi <pgeorgi@chromium.org> | 2016-02-19 17:33:26 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-02-21 12:26:05 +0100 |
| commit | a7cac0c21d85e651caaab2af7f8f1a7263e8abb9 (patch) | |
| tree | 24040626ebcc01f20efaeb06bc41650431fcbd84 /src/mainboard/emulation/qemu-riscv/bootblock.c | |
| parent | f92c3fb260e083d4548a4029548cf90675c6ec29 (diff) | |
soc/*: fix uart's regwidth specification in cbtables
coreboot passes information about the serial port implementation to
payloads through a cbtables entry.
We set the register width to 1 on most SoCs because that looked as good
a default as any, but checking the uart structs they use, it's 4 for all
of them.
Change-Id: I9848f79737106dc32f864ca901c0bc48f489e6b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13746
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/emulation/qemu-riscv/bootblock.c')
0 files changed, 0 insertions, 0 deletions