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authorMartin Roth <martin@coreboot.org>2021-10-01 14:37:30 -0600
committerMartin Roth <martinroth@google.com>2021-10-05 18:06:52 +0000
commit50863daef8ed75c0cb3dfd375e7622c898de5821 (patch)
treecbb2dea518524f8c9ce5edca5d57132ca9705086 /src/mainboard/emulation/qemu-q35
parent0949e739066c3509e05db2b9ed71cefaaa62205f (diff)
src/mainboard to src/security: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/emulation/qemu-q35')
-rw-r--r--src/mainboard/emulation/qemu-q35/bootblock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c
index 4a9a52fb42..ec86c70a3c 100644
--- a/src/mainboard/emulation/qemu-q35/bootblock.c
+++ b/src/mainboard/emulation/qemu-q35/bootblock.c
@@ -16,7 +16,7 @@ static void bootblock_northbridge_init(void)
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses.
+ * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.