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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-11 19:46:05 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-17 07:42:35 +0000 |
| commit | 20861b5ad3132f89a47bb07e711fb03d8d4ee254 (patch) | |
| tree | d42cd7533f9e3efe9a6fd66171c85e8950466c5c /src/mainboard/emulation/qemu-q35 | |
| parent | 9f5fea993ab0a9b9d59c00132c6ee58630b2481f (diff) | |
mb/emulation/qemu-q35: Release TSEG reserve with SMM_ASEG
If TSEG is not enabled, smm_region() should not reserve the region, so
add a test for T_EN flag in ESMRAMC.
For the SMM_ASEG case this moves CBMEM immediately below top-of-ram.
Change-Id: I2da4b846d0767afe00e98fdee375914c1875ddf5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/emulation/qemu-q35')
| -rw-r--r-- | src/mainboard/emulation/qemu-q35/memmap.c | 30 |
1 files changed, 20 insertions, 10 deletions
diff --git a/src/mainboard/emulation/qemu-q35/memmap.c b/src/mainboard/emulation/qemu-q35/memmap.c index e73e0dfa12..34656134ff 100644 --- a/src/mainboard/emulation/qemu-q35/memmap.c +++ b/src/mainboard/emulation/qemu-q35/memmap.c @@ -47,24 +47,33 @@ void mainboard_machine_check(void) #define TSEG_SZ_MASK (3 << 1) #define H_SMRAME (1 << 7) -void smm_region(uintptr_t *start, size_t *size) +/* Decodes TSEG region size to bytes. */ +static size_t decode_tseg_size(u8 esmramc) { - uint8_t esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC); + /* If we intent to enable TSEG, fake it always enabled. */ + if (CONFIG(SMM_TSEG)) + esmramc |= T_EN; + + if (!(esmramc & T_EN)) + return 0; switch ((esmramc & TSEG_SZ_MASK) >> 1) { case 0: - *size = 1 * MiB; - break; + return 1 * MiB; case 1: - *size = 2 * MiB; - break; + return 2 * MiB; case 2: - *size = 8 * MiB; - break; + return 8 * MiB; default: - *size = pci_read_config16(HOST_BRIDGE, EXT_TSEG_MBYTES) * MiB; + return pci_read_config16(HOST_BRIDGE, EXT_TSEG_MBYTES) * MiB; } +} +void smm_region(uintptr_t *start, size_t *size) +{ + uint8_t esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC); + + *size = decode_tseg_size(esmramc); *start = qemu_get_memory_size() * KiB - *size; printk(BIOS_SPEW, "SMM_BASE: 0x%08lx, SMM_SIZE: %zu MiB\n", *start, *size / MiB); } @@ -79,7 +88,8 @@ void smm_lock(void) printk(BIOS_DEBUG, "Locking SMM.\n"); if (CONFIG(SMM_TSEG)) - pci_or_config8(PCI_DEV(0, 0, 0), ESMRAMC, T_EN); + pci_or_config8(HOST_BRIDGE, ESMRAMC, T_EN); + pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG); } |